EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 240
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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9–20
Estimating Active Serial Configuration Time
Programming Serial Configuration Devices
Arria II GX Device Handbook, Volume 1
f
f
AS configuration time is dominated by the time it takes to transfer data from the serial
configuration device to the Arria II GX device. This serial interface is clocked by the
Arria II GX DCLK output (generated from an internal oscillator or an option to select
CLKUSR as external clock source). Arria II GX devices support DCLK up to 40 MHz
(25 ns).
Therefore, you can estimate the minimum configuration time as the following:
RBF Size × (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum
configuration time.
Enabling compression reduces the amount of configuration data that is transmitted to
the Arria II GX device, which also reduces configuration time. On average,
compression reduces configuration time, depending on your design.
Serial configuration devices are non-volatile, flash-memory-based devices. You can
program these devices in-system using an USB-Blaster™, EthernetBlaster, or
ByteBlaster™ II download cables. Alternatively, you can program them using a
microprocessor with the SRunner software driver.
You can perform in-system programming of serial configuration devices using the
conventional AS programming interface or JTAG interface solution.
Because serial configuration devices do not support the JTAG interface, the
conventional method to program them is using the AS programming interface. The
configuration data used to program serial configuration devices is downloaded using
programming hardware.
During in-system programming, the download cable disables device access to the AS
interface by driving the nCE pin high. Arria II GX devices are also held in reset mode
by a low level on nCONFIG. After programming is complete, the download cable
releases nCE and nCONFIG, allowing the pull-down and pull-up resistors to drive
GND and V
Altera has developed Serial FlashLoader (SFL); an in-system programming solution
for serial configuration devices using the JTAG interface. This solution requires the
Arria II GX device to be a bridge between the JTAG interface and the serial
configuration device.
For more information about SFL, refer to
Quartus II
For more information about the USB-Blaster download cable, refer to the
Download Cable User
to the
EthernetBlaster download cable, refer to the
Guide.
ByteBlaster II Download Cable User
Software.
CCIO
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
, respectively.
Guide. For more information about the ByteBlaster II cable, refer
Guide. For more information about the
AN 370: Using the Serial FlashLoader with
EthernetBlaster Communications Cable User
Active Serial Configuration (Serial Configuration Devices)
© July 2010 Altera Corporation
USB-Blaster
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