EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 100
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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5–8
Table 5–7. Mapping between Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs
Arria II GX Device Handbook, Volume 1
Clock Control Block Inputs
inclk[0], inclk[1]
inclk[2]
inclk[3]
Note to
(1) The left side of the Arria II GX device only allows PLL counter outputs as the dynamic clock source selection to the GCLK network. Therefore,
inclk[0] can be fed by PLL counters C4 or C6, while inclk[1] can only be fed by PLL counter C5.
Table
5–7:
1
Figure 5–4. Arria II GX GCLK Control Block
Notes to
(1) You can only dynamically control these clock select signals through internal logic when the device is operating in user
(2) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
(3) The left side of the Arria II GX device only allows PLL counter outputs as the dynamic clock source selection to the
(4) This is only available on the left side of the Arria II GX device.
Table 5–7
clock control block inputs.
When combining the PLL outputs and clock pins in the same clock control block,
ensure that these clock sources are implemented on the same side of the device.
For all possible legal inclk sources for each GCLK and RCLK network, refer to
Table 5–2 on page 5–5
(1)
mode.
controlled during user mode operation.
GCLK network.
Figure
Can be fed by any of the four dedicated clock pins on the same side
Can be fed by PLL counters C0 and C2 from the two corner PLLs on the same side of the
Arria II GX device
Can be fed by PLL counters C1 and C3 from the two corner PLLs on the same side of the
Arria II GX device
lists the mapping between the input clock pins, PLL counter outputs, and
5–4:
CLKSELECT[1..0]
PLL Counter
This multiplexer
supports user-controllable
dynamic switching
Outputs (3)
through
(1)
Table 5–6 on page
2
2
CLK
Pin
Description
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
2
Enable/
Disable
GCLK
CLK
5–7.
Pin
Block Clock Lines
Inter-Transceiver
Static Clock
Internal
Select (2)
Clock Networks in Arria II GX Devices
Logic
Internal
(4)
Logic
© July 2010 Altera Corporation
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