EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 251
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
JTAG Configuration
© July 2010
Altera Corporation
The Quartus II software verifies successful JTAG configuration after completion. At
the end of configuration, the software checks the state of CONF_DONE through the
JTAG port. When the Quartus II software generates a Jam
multi-device chain, it contains instructions so that all the devices in the chain are
initialized at the same time. If CONF_DONE is not high, the Quartus II software
indicates that configuration has failed. If CONF_DONE is high, the software indicates
that configuration was successful. After the configuration bitstream is transmitted
serially using the JTAG TDI port, the TCK port is clocked an additional 1,094 cycles to
perform device initialization.
Arria II GX devices have dedicated JTAG pins that always function as JTAG pins. Not
only can you perform JTAG testing on Arria II GX devices before and after, but also
during configuration. While other device families do not support JTAG testing during
configuration, Arria II GX devices support the bypass, ID code, and sample
instructions during configuration without interrupting configuration. All other JTAG
instructions may only be issued by first interrupting configuration and
reprogramming I/O pins using the CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured using the JTAG port
and when issued, interrupts configuration. This instruction allows you to perform
board-level testing prior to configuring the Arria II GX device or waiting for a
configuration device to complete configuration. After configuration is interrupted
and JTAG testing is complete, you must reconfigure the part using JTAG
(PULSE_CONFIG instruction) or by pulsing nCONFIG low.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on
Arria II GX devices do not affect JTAG boundary-scan or programming operations.
Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration of Arria II GX devices, consider the
dedicated configuration pins.
JTAG configuration.
Table 9–9. Dedicated Configuration Pin Connections During JTAG Configuration (Part 1 of 2)
nCE
nCEO
MSEL
nCONFIG
nSTATUS
Signal
On all Arria II GX devices in the chain, nCE must be driven low by connecting it to
ground, pulling it low using a resistor, or driving it by some control circuitry. For
devices that are also in multi-device FPP, AS, or PS configuration chains, the nCE
pins must be connected to GND during JTAG configuration, or JTAG must be
configured in the same order as the configuration chain.
On all Arria II GX devices in the chain, you can leave nCEO floating or connected
to nCE of the next device.
These pins must not be left floating. These pins support whichever non-JTAG
configuration is used in production. If you only use JTAG configuration, tie these
pins to GND.
Driven high by connecting to the V
resides, pulling up using a resistor, or driven high by some control circuitry.
Pull to the V
resistor. When configuring multiple devices in the same JTAG chain, each
nSTATUS pin must be pulled up to V
CCIO
power supply of the bank in which the pin resides using a 10-k
Table 9–9
lists how you must connect these pins during
Description
CCIO
CC IO
power supply of the bank in which the pin
individually.
TM
Arria II GX Device Handbook, Volume 1
file (.jam) for a
9–31
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