EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 118
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5–26
Arria II GX Device Handbook, Volume 1
1
Automatic Clock Switchover Mode
Use the switchover circuitry to automatically switch between inclk0 and inclk1
when the current reference clock to the PLL stops toggling. For example, in
applications that require a redundant clock with the same frequency as the reference
clock, the switchover state machine generates a signal (clksw) that controls the
multiplexer select input, as shown in
reference clock for the PLL. When you use the automatic switchover mode, you can
switch back and forth between the inclk0 and inclk1 clocks any number of times,
when one of the two clocks fails and the other clock is available.
When you use the automatic clock switchover mode, the following requirements
must be satisfied:
■
■
If the current clock input stops toggling while the other clock is also not toggling,
switchover is not initiated and the clkbad[0:1] signals are not valid. Also, if both
clock inputs are not the same frequency, but their period difference is 100%, the clock
sense block detects when a clock stops toggling, but the PLL may lose lock after the
switchover is completed and requires time to relock.
Altera recommends resetting the PLL with the areset signal to maintain the phase
relationships between the PLL input and output clocks when you use clock
switchover.
When you use automatic switchover mode, the clkbad[0] and clkbad[1] signals
indicate the status of the two clock inputs. When they are asserted, the clock sense
block has detected that the corresponding clock input has stopped toggling. These
two signals are not valid if the frequency difference between inclk0 and inclk1 is
greater than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or
inclk1) is being selected as the reference clock to the PLL. When the frequency
difference between the two clock inputs is more than 20%, the activeclock signal is
the only valid status signal.
Figure 5–20
switchover mode. In this example, the inclk0 signal is stuck low. After the inclk0
signal is stuck at low for approximately two clock cycles, the clock sense circuitry
drives the clkbad[0] signal high. Also, because the reference clock signal is not
toggling, the switchover state machine controls the multiplexer through the clksw
signal to switch to the backup clock, inclk1.
Both clock inputs must be running.
The period of the two clock inputs can differ by no more than 100% (2×).
shows an example waveform of the switchover feature with automatic
Figure
Chapter 5: Clock Networks and PLLs in Arria II GX Devices
5–19. In this case, inclk1 becomes the
© July 2010 Altera Corporation
PLLs in Arria II GX Devices
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