EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 192
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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8–8
Figure 8–4. Arria II GX Serializer Bypass Path
Notes to
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width to the IOE is 1 and 2, respectively.
Figure 8–5. Arria II GX LVDS Transmitter in Clock Output Mode
Arria II GX Device Handbook, Volume 1
Figure
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
8–4:
tx_coreclock
Differential applications often require specific clock-to-data alignments or a specific
data rate to clock rate factors. You can configure any Arria II GX LVDS transmitter to
generate a source-synchronous transmitter clock output. This flexibility allows the
placement of the output clock near the data outputs to simplify board layout and
reduce clock-to-data skew. The output clock can also be divided by a factor of 1, 2, 4, 6,
8, or 10, depending on the serialization factor. The phase of the clock in relation to the
data can be set at 0° or 180° (edge or center aligned). The center and corner PLLs
provide additional support for other phase shifts in 45° increments.
Figure 8–5
output mode, you can use an LVDS data channel as a clock output channel.
FPGA
Fabric
FPGA
Fabric
tx_in 10
shows the Arria II GX LVDS transmitter in clock output mode. In clock
Center/Corner PLL
DIN
center/
Serializer
corner
PLL
3
(Note
DOUT
Parallel
Transmitter Circuit
1), (2),
LVDS_LOAD_EN
2
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
diffioclk
IOE
Series
tx_inclock
(3)
LVDS Transmitter
IOE supports SDR, DDR, or
Non-Registered Datapath
LVDS Clock Domain
txclkout+
txclkout–
© July 2010 Altera Corporation
+
-
Differential Transmitter
tx_out
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