EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 165
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #3
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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Chapter 7: External Memory Interfaces in Arria II GX Devices
Arria II GX Memory Interfaces Pin Support
Figure 7–5. Number of DQ/DQS Groups per Bank in EP2AGX95 and EP2AGX125 Devices in the 572-Pin FineLine BGA
Package
Notes to
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a 4 DQ/DQS group with any of its pin members used for
(3) Arria II GX devices in the 572-pin FineLine BGA Package do not support 36 QDR II+/QDR II SRAM interface.
© July 2010 Altera Corporation
configuration purposes. Ensure that the DQ/DQS groups you have chosen are not also used for configuration.
Figure
(Note
7–5:
1), (2),
Figure 7–5
and EP2AGX125 devices in the 572-pin FineLine BGA package.
(3)
shows the number of DQ/DQS groups per bank in Arria II GX EP2AGX95
42 User I/Os
I/O Bank 8A
×16/×18=1
×32/×36=0
Devices in the 572-Pin FineLine BGA
38 User I/Os
×8/×9=2
I/O Bank 3A
×16/×18=1
×32/×36=0
×4=4
×8/×9=2
EP2AGX95 and EP2AGX125
×4=4
38 User I/Os
×16/×18=1
×32/×36=0
I/O Bank 4A
42 User I/Os
I/O Bank 7A
×8/×9=2
×16/×18=1
×32/×36=0
×8/×9=2
×4=4
×4=4
50 User I/Os
I/O Bank 6A
50 User I/Os
×16/×18=1
×32/×36=0
×16/×18=1
×32/×36=0
I/O Bank 5A
×8/×9=3
×8/×9=3
×4=6
×4=6
Arria II GX Device Handbook, Volume 1
7–7
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