EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 209
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Pin Placement Guidelines
Figure 8–22. Center PLLs Driving DPA-Enabled Differential I/Os
© July 2010
Altera Corporation
Using Both Center PLLs
You can use both center PLLs to drive DPA-enabled channels simultaneously, as long
as they drive these channels in their adjacent banks only, as shown in
If one of the center PLLs drives the DPA-enabled channels in the upper and lower I/O
banks, you cannot use the other center PLL for DPA, as shown in
If the upper center PLL drives DPA-enabled channels in the lower I/O bank, the
lower center PLL cannot drive DPA enabled channels in the upper I/O bank, and vice
versa. In other words, the center PLLs cannot drive cross-banks simultaneously, as
shown in
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Reference
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Center
CLK
CLK
PLL
PLL
Figure
8–23.
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
DPA-enabled
Reference
Reference
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Diff I/O
Diff I/O
Center
CLK
CLK
PLL
PLL
Arria II GX Device Handbook, Volume 1
Figure
Unused
Figure
PLL
8–22.
8–21.
8–25
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