EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 384

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Clock Modes
Clock Modes
2–16
Stratix Device Handbook, Volume 2
Implementing FIFO Buffers
While the small M512 memory blocks are ideal for designs with many
shallow FIFO buffers, all three memory sizes support FIFO mode.
All memory configurations have synchronous inputs; however, the FIFO
buffer outputs are always combinatorial. Simultaneous read and write
from an empty FIFO is not supported.
Depending on the TriMatrix memory mode, independent, input/output,
read/write, and/or single-port clock modes are available.
shows the clock modes supported by the TriMatrix memory modes.
Independent Clock Mode
The TriMatrix memory blocks can implement independent clock mode
for true dual-port memory. In this mode, a separate clock is available for
each port (A and B). Clock A controls all registers on the port A side,
while clock B controls all registers on the port B side. Each port also
supports independent clock enables and asynchronous clear signals for
port A and B registers.
independent clock mode.
Table 2–12. TriMatrix Memory Clock Modes
Clocking Mode
Independent
Input/output
Single-port
Read/write
Figure 2–9
True-Dual Port
Mode
v
v
shows a TriMatrix memory block in
Simple Dual-
Port Mode
v
v
Altera Corporation
Table 2–12
Single-Port
Mode
v
July 2005