EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 545
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 545 of 864
- Download datasheet (11Mb)
Altera Corporation
July 2005
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M512 Mode
Table 5–18. Address Counters for SERDES Bypass LVDS Receiver
Table 5–19. Address Counters for SERDES Bypass LVDS Transmitter
Table 5–20. Address & Counter Width
M512 Mode
M512 Mode
Write Counter
Width
Deserialization
Deserialization
4
5
6
5
Factor
Factor
16
16
4
8
8
4
8
8
For the transmitter, the read counter is the fast counter and the write
counter is the slow counter. For the receiver, the write counter is the fast
counter and the read counter is the slow counter.
provide the address counter configurations for the transmitter and the
receiver, respectively.
In different M512 memory configurations, the counter width is smaller
than the address width, so you must ground some of the most significant
address bits.
width, and the number of bits to be grounded.
Read Counter
Width
3
3
3
3
Width
Width
Write Up-Counter
Write Up-Counter
(Fast Counter)
(Fast Counter)
4
5
5
6
4
5
5
6
Table 5–20
Write Address
Width
High-Speed Differential I/O Interfaces in Stratix Devices
Starts at
Starts at
8
8
7
8
0
0
0
0
0
0
0
0
summarizes the address width, the counter
Read Address
Width
Width
Read Up-Counter
Read Up-Counter
(Slow Counter)
(Slow Counter)
Width
3
3
3
3
3
3
3
3
7
6
5
5
Stratix Device Handbook, Volume 2
Starts at
Starts at
Write Address Read Address
2
2
2
2
2
2
2
2
Number of Grounded Bits
Tables 5–18
4
3
1
3
Invalid Initial Cycles
Invalid Initial Cycles
Write
Write
12
24
24
48
2
2
2
2
and
Read
Read
4
3
2
2
5–19
16
6
6
6
6
4
8
8
5–73
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