EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 743
![IC STRATIX FPGA 40K LE 956-BGA](/photos/6/73/67334/544-stratix_956-bga_sml.jpg)
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 11–11. FPP Configuration with a Configuration Device Timing Waveform
Notes to
(1)
(2)
(3)
Altera Corporation
July 2005
nINIT_CONF or VCC/nCONFIG
For timing information, see the Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet.
The configuration device drives DATA high after configuration.
Stratix and Stratix GX devices enter user mode 136 clock cycles after CONF_DONE goes high.
Figure
nCS/CONF_DONE
OE/nSTATUS
INIT_DONE
11–11:
DATA[7..0]
User I/O
DCLK
t
OEZX
FPP Configuration Using a Microprocessor
When using a microprocessor for parallel configuration, the
microprocessor transfers data from a storage device to the Stratix or
Stratix GX device through configuration hardware. To initiate
configuration, the microprocessor needs to generate a low-to-high
transition on the nCONFIG pin and the Stratix or Stratix GX device must
release nSTATUS. The microprocessor then places the configuration data
to the DATA[7..0] pins of the Stratix or Stratix GX device. Data is
clocked continuously into the Stratix or Stratix GX device until
CONF_DONE goes high.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists. You can pause configuration by halting DCLK for an indefinite
amount of time.
After all configuration data is sent to the Stratix or Stratix GX device, the
CONF_DONE pin goes high to show successful configuration and the start
of initialization. The CONF_DONE pin must have an external 10-k pull-
up resistor in order for the device to initialize. Initialization, by default,
uses an internal oscillator, which runs at 10 MHz. After initialization, this
internal oscillator is turned off. If you are using the clkusr option, after all
data is transferred clkusr must be clocked an additional 136 times for
the Stratix or Stratix GX device to initialize properly. Driving DCLK to the
device after configuration is complete does not affect device operation. By
t
CO
Tri-State
t
t
Byte0 Byte1
POR
DSU
t
CL
Byte2 Byte3
t
DH
t
CH
Byten
Tri-State
Configuring Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
(3)
Note (1)
User Mode
(2)
11–25
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