EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 520
EP1S40B956C5
Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S40B956C5
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40B956C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- Current page: 520 of 864
- Download datasheet (11Mb)
Differential I/O Termination
Figure 5–35. PCML Differential Termination
5–48
Stratix Device Handbook, Volume 2
Transmitter
Differential
50 Ω
Differential HSTL Termination
The HSTL Class I and II I/O standards require a 0.75-V V
V V
termination for HSTL Class I and II I/O standard.
Figure 5–36. Differential HSTL Class I Termination
TT
Transmitter
.
Differential
Figures 5–36
50 Ω
and
Z
Z
0
0
= 50 Ω
= 50 Ω
Z
Z
5–37
0
0
= 50 Ω
= 50 Ω
50 Ω
show the device with differential
V
50 Ω
TT
V
TT
= 0.75 V
50 Ω
50 Ω
V
TT
= 0.75 V
Differential
Receiver
Altera Corporation
REF
Differential
Receiver
and a 0.75-
July 2005
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