EP2SGX90EF1152C5ES Altera, EP2SGX90EF1152C5ES Datasheet - Page 208
EP2SGX90EF1152C5ES
Manufacturer Part Number
EP2SGX90EF1152C5ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C5ES
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1765
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 208 of 316
- Download datasheet (2Mb)
Operating Conditions
4–38
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Serial RapidIO
SDI
BASIC Single
Width
BASIC Double
Width
Table 4–21. PCS Latency (Part 2 of 2)
Functional Mode
The latency numbers are with respect to the PLD-transceiver interface clock cycles.
The total latency number is rounded off in the Sum column.
For CPRI 614 Mbps and 1.228 Gbps data rates, the Quartus II software customizes the PLD-transceiver
interface clocking to achieve zero clock cycle uncertainty in the transmitter phase compensation FIFO
latency. For more details, refer to the CPRI Mode section in the
chapter in volume 2 of the Stratix II GX Device Handbook.
Table
4–21:
10-bit channel
20-bit channel
Configuration
channel width
channel width
channel width
channel width
16-bit/20-bit
16-bit/20-bit
32-bit/40-bit
3.125 Gbps
1.25 Gbps,
8-bit/10-bit
Loopback/
2.5 Gbps,
HD, 3G
Parallel
width
width
BIST
HD
TX PIPE
Note (1)
-
-
-
-
-
-
-
-
Phase
Comp
FIFO
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
TX
Transmitter PCS Latency
Serializer
Byte
Stratix II GX Transceiver Architecture Overview
1
1
1
1
1
1
1
1
TX State
Machine
-
-
-
-
-
-
-
-
Encoder
8B/10B
0.5
0.5
0.5
0.5
1
1
1
1
Altera Corporation
Sum
4-5
4-5
4-5
4-5
4-5
4-5
4-5
4-5
(2)
June 2009
Related parts for EP2SGX90EF1152C5ES
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: