EP2SGX90EF1152C5ES Altera, EP2SGX90EF1152C5ES Datasheet - Page 227

IC STRATIX II GX 90K 1152-FBGA

EP2SGX90EF1152C5ES

Manufacturer Part Number
EP2SGX90EF1152C5ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90EF1152C5ES

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1765

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90EF1152C5ES
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX90EF1152C5ES
Manufacturer:
ALTERA
0
Altera Corporation
June 2009
Note for
(1)
(2)
50-Ω R
2.5
25-Ω R
1.8
50-Ω R
1.8
50-Ω R
1.8
50-Ω R
1.5
50-Ω R
1.5
50-Ω R
1.2
50-Ω R
1.2
Table 4–49. On-Chip Termination Specification for Top and Bottom I/O Banks (Part 2 of 2)
Symbol
The resistance tolerance for calibrated SOCT is for the moment of calibration. If the temperature or voltage changes
over time, the tolerance may also change.
On-chip parallel termination with calibration is only supported for input pins.
T
S
S
T
S
T
S
T
Table
Internal parallel termination with
calibration (50-Ω setting)
Internal series termination with
calibration (25-Ω setting)
Internal series termination without
calibration (25-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
Internal series termination with
calibration (50-Ω setting)
Internal series termination without
calibration (50-Ω setting)
Internal parallel termination with
calibration (50-Ω setting)
4–49:
Description
V
V
V
V
V
V
V
V
V
V
V
V
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
Conditions
= 1.8 V
= 1.8 V
= 1.8 V
= 1.8 V
= 1.8 V
= 1.8 V
= 1.5 V
= 1.5 V
= 1.5 V
= 1.2 V
= 1.2 V
= 1.2 V
Stratix II GX Device Handbook, Volume 1
Commercial
DC and Switching Characteristics
Max
±10
±10
±10
±30
±30
±30
±36
±50
±8
±5
±5
±8
Resistance Tolerance
Industrial
Max
± 30
±15
±15
±15
±10
±30
±10
±30
±10
±36
±10
±50
Notes
(1),
Unit
%
%
%
%
%
%
%
%
%
%
%
%
4–57
(2)

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