XCS30XL-4VQ100I Xilinx Inc, XCS30XL-4VQ100I Datasheet - Page 29

• Manufacturer Part Number: XCS30XL-4VQ100I
• Description: IC FPGA 3.3V I-TEMP HP 100VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS30XL-4VQ100I

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 77
• Number Of Gates: 30000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Express Mode (Spartan-XL Family Only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers
quency of 1 MHz is equivalent to a 8 MHz serial rate,
because eight bits of configuration data are loaded per
CCLK cycle. Express mode does not support CRC error
checking, but does support constant-field error checking. A
length count is not used in Express mode.
Express mode must be specified as an option to the devel-
opment system. The Express mode bitstream is not com-
patible with the other configuration modes (see
page
pins (M1, M0).
The first byte of parallel configuration data must be available
at the D inputs of the FPGA a short setup time before the
second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge
(Figure
Pseudo Daisy Chain
Multiple devices with different configurations can be config-
ured in a pseudo daisy chain provided that all of the devices
DS060 (v1.8) June 26, 2008
Product Specification
(Output)
32.) Express mode is selected by a <0X> on the Mode
DOUT
CCLK
28).
DIN
R
Notes:
1.
Symbol
Figure 26: Slave Serial Mode Programming Switching Characteristics
T
T
T
T
T
Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are
High.
F
CCO
DCC
CCD
CCH
CCL
CC
T
DCC
(Figure
Bit n
CCLK
27). A CCLK fre-
T
CCD
DIN setup
DIN hold
DIN to DOUT
High time
Low time
Frequency
Table 16,
Bit n – 1
Description
www.xilinx.com
T
CCH
are in Express mode. Concatenated bitstreams are used to
configure the chain of Express mode devices so that each
device receives a separate header. CCLK pins are tied
together and D0-D7 pins are tied together for all devices
along the chain. A status signal is passed from DOUT to
CS1 of successive devices along the chain. Frame data is
accepted only when CS1 is High and the device’s configura-
tion memory is not already full. The lead device in the chain
has its CS1 input tied High (or floating, since there is an
internal pull-up). The status pin DOUT is pulled Low after
the header is received, and remains Low until the device’s
configuration memory is full. DOUT is then pulled High to
signal the next device in the chain to accept the next header
and configuration data on the D0-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a large
number of devices are included in the chain, deactivate
some of the internal pull-ups, since the Low-driving DONE
pin of the last device in the chain must sink the current from
all pull-ups in the chain. The DONE pull-up is activated by
default. It can be deactivated using a development system
option.
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All Spartan-XL devices in Express mode are synchronized
Spartan and Spartan-XL FPGA Families Data Sheet
Bit n + 1
Min
20
40
40
0
-
-
T
CCO
Max
12.5
30
-
-
-
-
T
CCL
Units
MHz
ns
ns
ns
ns
ns
Bit n
DS060_26_080400
29