XCS30XL-4VQ100I Xilinx Inc, XCS30XL-4VQ100I Datasheet - Page 46

• Manufacturer Part Number: XCS30XL-4VQ100I
• Description: IC FPGA 3.3V I-TEMP HP 100VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS30XL-4VQ100I

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 77
• Number Of Gates: 30000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan and Spartan-XL FPGA Families Data Sheet
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
(continued)
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Spartan Family CLB RAM Synchronous (Edge-Triggered) Write Timing
Single Port
46
Notes:
1.
DATA OUT
Write Operation
ADDRESS
WCLK (K)
DATA IN
Symbol
T
T
T
T
T
T
T
T
T
Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
WODS
WCDS
WPDS
WSDS
WHDS
ASDS
AHDS
DSDS
DHDS
WE
T
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Address write cycle time (clock K period)
ILO
T
T
T
WSS
DSS
ASS
T
WOS
OLD
Dual Port RAM
T
WPS
T
T
T
NEW
AHS
WHS
DHS
www.xilinx.com
T
ILO
in the Xilinx Development System) and back-annotated to
the simulation netlist. All timing parameters assume
worst-case operating conditions (supply voltage and junc-
tion temperature). Values apply to all Spartan devices and
are expressed in nanoseconds unless otherwise noted.
DATA OUT
ADDRESS
WCLK (K)
DATA IN
Dual Port
WE
Size
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
T
ILO
(1)
Min
8.0
4.0
1.5
1.5
1.5
0
0
0
-
T
T
T
DSDS
ASDS
WSDS
-4
Max
T
6.5
WODS
-
-
-
-
-
-
-
-
DS060 (v1.8) June 26, 2008
OLD
11.6
Min
Product Specification
5.8
2.1
1.6
1.6
0
0
0
-
-3
T
WPDS
Max
7.0
T
T
T
-
-
-
-
-
-
-
-
NEW
WHDS
T
AHDS
DHDS
DS060_34_011300
ILO
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
R