XCS30XL-4VQ100I Xilinx Inc, XCS30XL-4VQ100I Datasheet - Page 64

• Manufacturer Part Number: XCS30XL-4VQ100I
• Description: IC FPGA 3.3V I-TEMP HP 100VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS30XL-4VQ100I

• Number Of Logic Elements/cells: 1368
• Number Of Labs/clbs: 576
• Total Ram Bits: 18432
• Number Of I /o: 77
• Number Of Gates: 30000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Spartan and Spartan-XL FPGA Families Data Sheet
Table 18: Pin Descriptions (Continued)
64
Unrestricted User-Programmable I/O Pins
(Spartan-XL)
(Spartan-XL)
(Spartan-XL)
Pin Name
(Spartan)
SGCK1 -
SGCK4
GCK1 -
D0-D7
DOUT
GCK8
CS1
DIN
I/O
is DOUT)
GCK6 is
Config.
SGCK4
(except
(except
During
DOUT)
Pull-up
Pull-up
Pull-up
Weak
Weak
Weak
I/O
O
I
I
I
I/O After
Config.
I or I/O
I or I/O
I/O
I/O
I/O
I/O
I/O
Four Secondary Global inputs each drive a dedicated internal global net with short
delay and minimal skew. These internal global nets can also be driven from
internal logic. If not used to drive a global net, any of these pins is a
user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global
Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol
is automatically placed on one of these pins.
Eight Global inputs each drive a dedicated internal global net with short delay and
minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew
Buffers. Any input pad symbol connected directly to the input of a BUFGLS symbol
is automatically placed on one of these pins.
During Express configuration, CS1 is used as a serial-enable signal for
daisy-chaining.
During Express configuration, these eight input pins receive configuration data.
After configuration, they are user-programmable I/O pins.
During Slave Serial or Master Serial configuration, DIN is the serial configuration
data input receiving data on the rising edge of CCLK. After configuration, DIN is a
user-programmable I/O pin.
During Slave Serial or Master Serial configuration, DOUT is the serial
configuration data output that can drive the DIN of daisy-chained slave FPGAs.
DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods
after it was received at the DIN input.
In Spartan-XL family Express mode, DOUT is the status output that can drive the
CS1 of daisy-chained FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
These pins can be configured to be input and/or output after configuration is
completed. Before configuration is completed, these pins have an internal
high-value pull-up resistor network that defines the logic level as High.
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Pin Description
DS060 (v1.8) June 26, 2008
Product Specification
R