XC4VLX25-11FFG668C Xilinx Inc, XC4VLX25-11FFG668C Datasheet

IC FPGA VIRTEX-4 24K 668-FCBGA

XC4VLX25-11FFG668C

Manufacturer Part Number
XC4VLX25-11FFG668C
Description
IC FPGA VIRTEX-4 24K 668-FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VLX25-11FFG668C

Number Of Logic Elements/cells
24192
Number Of Labs/clbs
2688
Total Ram Bits
1327104
Number Of I /o
448
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
Package
668FCBGA
Family Name
Virtex®-4
Device Logic Units
24192
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
448
Ram Bits
1327104
For Use With
807-1004 - DAUGHTER CARD WITH VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668122-1523 - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
122-1490

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DS302 (v3.7) September 9, 2009
Virtex-4 FPGA Electrical Characteristics
Virtex®-4 FPGAs are available in -12, -11, and -10 speed
grades, with -12 having the highest performance.
Virtex-4 FPGA DC and AC characteristics are specified for
both commercial and industrial grades. Except the operat-
ing temperature range or unless otherwise noted, all the DC
and AC electrical parameters are the same for a particular
speed grade (that is, the timing characteristics of a -10
speed grade industrial device are the same as for a -10
speed grade commercial device). However, only selected
speed grades and/or devices might be available in the
industrial range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parame-
ters included are common to popular designs and typical
applications.
Virtex-4 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings
© 2004–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other
trademarks are the property of their respective owners.
DS302 (v3.7) September 9, 2009
Product Specification
Symbol
V
V
V
V
V
CCAUX
CCINT
V
BATT
CCO
I
REF
IN
IN
Internal supply voltage relative to GND
Auxiliary supply voltage relative to GND
Output drivers supply voltage relative to GND
Key memory battery backup supply
Input reference voltage
I/O input voltage relative to GND
(all user and dedicated I/Os)
I/O input voltage relative to GND
(restricted to maximum of 100 user I/Os)
2.5V or below I/O input voltage relative to GND
(user and dedicated I/Os)
Current applied to an I/O pin, powered or unpowered
Total current applied to all I/O pins, powered or unpowered
Description
0
0
www.xilinx.com
(3,4)
0
Virtex-4 FPGA Data Sheet:
DC and Switching Characteristics
Product Specification
This Virtex-4 FPGA Data Sheet is part of an overall set of
documentation on the Virtex-4 family of FPGAs that is avail-
able on the Xilinx website:
All specifications are subject to change without notice.
Virtex-4 Family Overview,
Virtex-4 FPGA User Guide,
Virtex-4 FPGA Configuration Guide,
XtremeDSP for Virtex-4 FPGAs User Guide,
Virtex-4 FPGA Packaging and Pinout Specification,
UG075
Virtex-4 FPGA PCB Designer’s Guide,
Virtex-4 RocketIO™ Multi-Gigabit Transceiver User
Guide,
Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC
User Guide,
PowerPC® 405 Processor Block Reference Guide,
UG018
UG076
UG074
(Commercial Temperature)
(Industrial Temperature)
–0.75 to V
DS112
UG070
–0.75 to 4.05
–0.5 to 1.32
–0.5 to 3.75
–0.5 to 4.05
–0.3 to 3.75
–0.85 to 4.3
–0.95 to 4.4
–0.5 to 3.0
±100
±200
CCO
UG071
UG072
+0.5
UG073
Units
mA
mA
V
V
V
V
V
V
V
V
1

Related parts for XC4VLX25-11FFG668C

XC4VLX25-11FFG668C Summary of contents

Page 1

DS302 (v3.7) September 9, 2009 Virtex-4 FPGA Electrical Characteristics Virtex®-4 FPGAs are available in -12, -11, and -10 speed grades, with -12 having the highest performance. Virtex-4 FPGA DC and AC characteristics are specified for both commercial and industrial grades. ...

Page 2

Table 1: Absolute Maximum Ratings (Continued) Symbol Voltage applied to 3-state 3.3V output (all user and dedicated I/Os) Voltage applied to 3-state 3.3V output V TS (restricted to maximum of 100 user I/Os) 2.5V or below I/O input voltage relative ...

Page 3

Table 2: Recommended Operating Conditions (Continued) Symbol (6) AVCCAUXRX Auxiliary receive supply voltage relative to GNDA (6) AVCCAUXTX Auxiliary transmit supply voltage relative to GNDA AVCCAUXMGT Auxiliary management supply voltage relative to GNDA (7) V Terminal receive supply voltage relative ...

Page 4

... MGTs operating with CC (1) Device Typ Max XC4VLX15 46 Note (6) XC4VLX25 77 Note (6) XC4VLX40 121 Note (6) XC4VLX60 167 Note (6) XC4VLX80 220 Note (6) XC4VLX100 292 Note (6) XC4VLX160 384 Note (6) XC4VLX200 489 ...

Page 5

... XC4VSX55 1.5 Note (6) XC4VFX12 1.25 Note (6) XC4VFX20 1.25 Note (6) XC4VFX40 1.25 Note (6) XC4VFX60 1.5 Note (6) XC4VFX100 1.75 Note (6) XC4VFX140 2.5 Note (6) XC4VLX15 31 Note (6) XC4VLX25 36 Note (6) XC4VLX40 43 Note (6) XC4VLX60 74 Note (6) XC4VLX80 83 Note (6) XC4VLX100 95 Note (6) XC4VLX160 133 Note (6) XC4VLX200 150 Note (6) XC4VSX25 62 Note (6) ...

Page 6

Table 4: Quiescent Supply Current (Continued) Symbol (4) I Quiescent AVCCAUXTX supply current CCAUXTX (4,5) I Quiescent V supply current TTX TTX (4,5) I Quiescent V supply current TRX TRX (4) Quiescent V I AUXMGT AUXMGT Notes: 1. Typical values ...

Page 7

... V Xilinx does not specify the current for other power-on sequences. Table 5: Power-On Current for Virtex-4 Devices I CCINTMIN (1) Device Typ Max XC4VLX15 110 XC4VLX25 160 XC4VLX40 250 XC4VLX60 300 XC4VLX80 400 XC4VLX100 500 XC4VLX160 700 XC4VLX200 ...

Page 8

SelectIO™ DC Input and Output Levels Values for V and V are recommended input voltages Values for I and I are guaranteed over the recom mended operating conditions at the V points. Only selected standards are ...

Page 9

LDT DC Specifications (LDT_25) Table 8: LDT DC Specifications Symbol DC Parameter V Supply Voltage CCO V Differential Output Voltage OD Δ V Change in V Magnitude Output Common Mode Voltage OCM Δ V Change in V ...

Page 10

Extended LVDS DC Specifications (LVDSEXT_25) Table 10: Extended LVDS DC Specifications Symbol DC Parameter V Supply Voltage CCO V Output High Voltage for Q and Output Low Voltage for Q and Q OL Differential Output Voltage (Q ...

Page 11

RocketIO DC Input and Output Levels Table 12 summarizes the DC input and output specifica- tions of the Virtex-4 FPGA RocketIO Multi-Gigabit Serial Transceivers. Figure 1 shows the single-ended output volt- Table 12: RocketIO DC Specifications DC Parameter Peak-to-Peak Differential ...

Page 12

... MHz 1 Gb/s (2) 600 Mb/s (3) 420 Mb/s (4) 550 Mb/s (5) 344 Mb/s (6) 470 Mb/s Table 14: Virtex-4 Device Speed Grade Designations Device Advance XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 XC4VFX60 XC4VFX100 XC4VFX140 www.xilinx.com Speed Grade ...

Page 13

Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. Testing of Switching Characteristics All devices are 100% functionally tested. Internal timing ...

Page 14

Table 16: Processor Block Switching Characteristics Description Setup and Hold Relative to Clock (CPMC405CLOCK) Clock and Power Management control inputs Reset control inputs Debug control inputs Trace control inputs External Interrupt Controller control inputs Clock to Out Clock and Power ...

Page 15

Table 19: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics Description Setup and Hold Relative to Clock (BRAMDSOCMCLK) Data-Side On-Chip Memory data bus inputs Clock to Out Data-Side On-Chip Memory control outputs Data-Side On-Chip Memory address bus outputs T Data-Side On-Chip ...

Page 16

Table 22: Processor Block APU Interface Switching Characteristics Description Setup and Hold Relative to Clock (CPMDFCMCLOCK) APU bus control inputs APU bus data inputs Clock to Out APU bus control outputs APU bus data outputs RocketIO Switching Characteristics Consult the ...

Page 17

Table 25: RocketIO Receiver Switching Characteristics Description Serial data rate, -10 Serial data rate, -11 XAUI Receive Jitter Tolerance (8B/10B CJPAT) Receive Deterministic Jitter Tolerance Receive Total Jitter Tolerance Receive Sinusoidal Jitter Tolerance General Receive Jitter Tolerance Receive deterministic jitter ...

Page 18

Table 26: RocketIO Transmitter Switching Characteristics Description Serial data rate, -10 Serial data rate, -11 (3) TX Jitter Generation (2) TX rise time (2) TX fall time TXUSRCLK frequency TXUSRCLK2 frequency TXUSRCLK duty cycle TXUSRCLK2 duty cycle Differential output skew ...

Page 19

IOB Pad Input/Output/3-State Switching Characteristics Table 27 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard and 3-state delays described as the delay from IOB pad through the IOPI input ...

Page 20

Table 27: IOB Switching Characteristics IOSTANDARD (1) Attribute -12 LVTTL, Slow 0.76 LVTTL, Slow 0.76 LVTTL, Slow 0.76 LVTTL, Fast 0.76 LVTTL, Fast 0.76 LVTTL, Fast 0.76 LVTTL, ...

Page 21

Table 27: IOB Switching Characteristics IOSTANDARD (1) Attribute -12 LVCMOS25, Fast 0.69 LVCMOS25, Fast 0.69 LVCMOS18, Slow 0.97 LVCMOS18, Slow 0.97 LVCMOS18, Slow 0.97 LVCMOS18, Slow 0.97 LVCMOS18, ...

Page 22

Table 27: IOB Switching Characteristics IOSTANDARD (1) Attribute -12 (3) HSTL_II_DCI 1.28 (3) HSTL_III_DCI 1.28 (3) HSTL_IV_DCI 1.28 (3) HSTL_I_DCI_18 1.26 (3) HSTL_II_DCI_18 1.26 (3) HSTL_III_DCI_18 1.26 (3) HSTL_IV_DCI_18 1.26 (3) SSTL2_I_DCI 1.31 (3) SSTL2_II_DCI 1.31 LVPECL_25 1.38 SSTL18_I 1.31 ...

Page 23

I/O Standard Adjustment Measurement Methodology Input Delay Measurements Table 30 shows the test setup parameters used for measuring input delay. Table 30: Input Delay Measurement Methodology Description LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, ...

Page 24

Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4 inches of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4 inch trace is ...

Page 25

Table 31: Output Delay Measurement Methodology (Continued) Description HSTL, Class IV, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V LVDS (Low-Voltage Differential Signaling), 2.5V LVDSEXT (LVDS Extended ...

Page 26

Input/Output Logic Switching Characteristics Table 32: ILOGIC Switching Characteristics Symbol Setup/Hold / T T CE1 pin Setup/Hold with respect to CLK ICE1CK ICKCE1 / T T DLYCE pin Setup/Hold with respect to C ICECK ICKCE / T T DLYRST pin ...

Page 27

Table 33: OLOGIC Switching Characteristics Symbol Setup/Hold / T T D1/D2 pins Setup/Hold with respect to CLK ODCK OCKD / T T OCE pin Setup/Hold with respect to CLK OOCECK OCKOCE / T T SR/REV pin Setup/Hold with respect to ...

Page 28

Input Serializer/Deserializer Switching Characteristics Table 34: ISERDES Switching Characteristics Symbol Setup/Hold for Control Lines / T T ISCCK_BITSLIP ISCKC_BITSLIP ( ISCCK_CE ISCKC_CE ( ISCCK_CE2 ISCKC_CE2 / T T ISCCK_DLYCE ISCKC_DLYCE / T T ISCCK_DLYINC ...

Page 29

Input Delay Switching Characteristics Table 35: Input Delay Switching Characteristics Symbol IDELAYCTRL Reset to Ready for IDELAYCTRL T IDELAYCTRLCO_RDY (Maximum) F REFCLK frequency IDELAYCTRL_REF (2) REFCLK precision IDELAYCTRL_REF_PRECISION T Minimum Reset pulse width IDELAYCTRL_RPW IDELAY T IDELAY Chain Delay Resolution ...

Page 30

Output Serializer/Deserializer Switching Characteristics Table 36: OSERDES Switching Characteristics Symbol Setup/Hold / input Setup/Hold with respect to CLKDIV OSDCK_D OSCKD_D ( input Setup/Hold with respect to CLK OSDCK_T OSCKD_T ( ...

Page 31

CLB Switching Characteristics Table 37: CLB Switching Characteristics Symbol Combinatorial Delays T 4-input function: F/G inputs to X/Y outputs ILO T 5-input function: F/G inputs to F5 output IF5 T 5-input function: F/G inputs to X output IF5X T FXINA ...

Page 32

CLB Distributed RAM Switching Characteristics (SLICEM Only) ) Table 38: CLB Distributed RAM Switching Characteristics Symbol Sequential Delays T Clock CLK to X outputs (WE active) SHCKO T Clock CLK to F5 output (WE active) SHCKOF5 Setup and Hold Times ...

Page 33

Block RAM and FIFO Switching Characteristics Table 40: Block RAM Switching Characteristics Symbol Sequential Delays Clock CLK to DOUT output (without output register) T Clock CLK to DOUT output with ECC RCKO_DORA (without output register) Clock CLK to DOUT output ...

Page 34

Table 41: FIFO Switching Characteristics Symbol Sequential Delays T Clock CLK to DO output FCKO_DO T Clock CLK to FIFO flags outputs FCKO_FLAGS T Clock CLK to FIFO pointer outputs FCKO_POINTERS Setup and Hold Times Before Clock CLK / T ...

Page 35

XtremeDSP™ Switching Characteristics Table 42: XtremeDSP Switching Characteristics Symbol Setup and Hold of CE Pins / T T Setup/Hold of all CE inputs of the DSP48 slice DSPCCK_CE DSPCKC_CE / T T Setup/Hold of all RST inputs of the DSP48 ...

Page 36

Configuration Switching Characteristics Table 43: Configuration Switching Characteristics Symbol Power-up Timing Characteristics (1,2) T CONFIG POR T ICCK T PROGRAM Master/Slave Serial Mode Programming Switching / T T DCC CCD / T T DSCK SCKD T CCO ...

Page 37

Table 43: Configuration Switching Characteristics (Continued) Symbol Boundary-Scan Port Timing Specifications T TAPTCK T TCKTAP T TCKTDO F TCK F TCKB Dynamic Reconfiguration Port (DRP) for DCM CLKIN_FREQ_DLL_HF_MS_MAX T /T DMCCK_DADDR DMCKC_DADDR T /T DMCCK_DI DMCKC_DI T /T DMCCK_DEN DMCKC_DEN ...

Page 38

Clock Buffers and Networks Table 44: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol ( pins Setup/Hold BCCCK_CE BCCKC_CE ( pins Setup/Hold BCCCK_S BCCKC_S T BUFGCTRL delay BCCKO_O Maximum Frequency F Global clock ...

Page 39

Table 45: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Continued) Symbol CLKOUT_FREQ_FX_HF_MS_MIN CLKOUT_FREQ_FX_HF_MS_MAX Input Clocks (High Frequency Mode) (6) CLKIN_FREQ_DLL_HF_MS_MIN CLKIN_FREQ_DLL_HF_MS_MAX CLKIN_FREQ_FX_HF_MS_MIN (6) CLKIN_FREQ_FX_HF_MS_MAX PSCLK_FREQ_HF_MS_MIN PSCLK_FREQ_HF_MS_MAX Notes: 1. DLL outputs are used in these instances to describe ...

Page 40

Table 47: Input Clock Tolerances Symbol Duty Cycle Input Tolerance (in %) CLKIN_PSCLK_PULSE_RANGE_1 CLKIN_PSCLK_PULSE_RANGE_1_50 CLKIN_PSCLK_PULSE_RANGE_50_100 CLKIN_PSCLK_PULSE_RANGE_100_200 CLKIN_PSCLK_PULSE_RANGE_200_400 CLKIN_PSCLK_PULSE_RANGE_400 Input Clock Cycle-Cycle Jitter (Low Frequency Mode) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_FX_LF Input Clock Cycle-Cycle Jitter (High Frequency Mode) CLKIN_CYC_JITT_DLL_HF CLKIN_CYC_JITT_FX_HF Input Clock Period Jitter ...

Page 41

Output Clock Jitter Table 48: Output Clock Jitter Description Clock Synthesis Period Jitter CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180 Notes: 1. PMCD outputs are not included in this table because they do ...

Page 42

Table 50: Miscellaneous Timing Parameters Symbol Time Required to Achieve LOCK T_LOCK_DLL_240 T_LOCK_DLL_120_240 T_LOCK_DLL_60_120 T_LOCK_DLL_50_60 T_LOCK_DLL_40_50 T_LOCK_DLL_30_40 T_LOCK_DLL_24_30 T_LOCK_DLL_30 T_LOCK_FX_MAX T_LOCK_DLL_FINE_SHIFT Fine Phase Shifting FINE_SHIFT_RANGE_MS FINE_SHIFT_RANGE_MR Delay Lines DCM_TAP_MS_MIN DCM_TAP_MS_MAX DCM_TAP_MR_MIN DCM_TAP_MR_MAX Input Signal Requirements (4) DCM_RESET DCM_INPUT_CLOCK_STOP Notes: 1. ...

Page 43

Table 51: Frequency Synthesis Attribute CLKFX_MULTIPLY CLKFX_DIVIDE Table 52: DCM Switching Characteristics Symbol / T T DMCCK_PSEN DMCKC_PSEN / T T DMCCK_PSINCDEC DMCKC_PSINCDEC T DMCKO_PSDONE Table 53: PMCD Switching Characteristic Symbol / T T PMCCCK_REL PMCCKC_REL T PMCCO_CLK{A1,B,C,D} T PMCCKO_CLK{A1,B,C,D} ...

Page 44

... IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation. DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 ...

Page 45

... Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 ...

Page 46

... IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards. DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description Device (2) with DCM XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 ...

Page 47

... IFF = Input Flip-Flop DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description (1,2) , page 19. (2) with DCM in XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 ...

Page 48

... A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed, there is no positive hold time. DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description XC4VLX15 (2) without DCM XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 ...

Page 49

... I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to your application. DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) (2) XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 ...

Page 50

... Package trace length information is available for these device/package combinations. This information can be used to deskew the package. DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 ...

Page 51

... JTAG ID code by step. DS302 (v3.7) September 9, 2009 Product Specification Virtex-4 FPGA Data Sheet: DC and Switching Characteristics Description Device (1) (2) Description Table 63: JTAG ID Code by Step Device XC4VLX15 XC4VLX25 XC4VLX40 XC4VLX60 XC4VLX80 XC4VLX100 XC4VLX160 XC4VLX200 XC4VSX25 XC4VSX35 XC4VSX55 XC4VFX12 XC4VFX20 XC4VFX40 ...

Page 52

Current Virtex-4 Production Devices Table 64 summarizes the current production LX and SX device stepping. Table 64: Current LX and SX Production Devices LX/SX Device Stepping Example Ordering Code Device steppings shipped when ordered per Example Ordering Code (1) Capability ...

Page 53

Revision History The following table shows the revision history for this document. Date Version 08/02/04 1.0 Initial Xilinx release. Printed Handbook version. 09/09/04 1.1 Edits in Tables 12, 13, 18, 19, 20, 22, 26, 28, 37, and 38. Removed Table ...

Page 54

Date Version 02/03/06 1.11 Revised the speed specification requirements in parameter changes in and I Table Table 600 mV and added a new Note 1. Also in specification from 95mV to 950mV. Changed performance numbers in the typical specification for ...

Page 55

Date Version 09/07/06 1.16 Added 2.5V rows to V 110 mV in Table T IDELAYTOTAL_ERR 10/06/06 1.17 • • • • • • 12/11/06 2.0 • • • • • • • • • • • • • • • ...

Page 56

Date Version 12/11/06 2.0 • (Cont’d) (Cont’d) • • 03/27/07 2.1 • • • • • • • • • • • 06/08/07 2.2 • • • • • • 08/10/07 2.3 • • • • • • • • ...

Page 57

Date Version 09/28/07 3.0 • • • • • • 12/11/07 3.1 • • • • • • • • • • • 04/10/08 3.2 • • • • 06/06/08 3.3 • • • • 11/26/08 3.4 • 06/16/09 3.5 ...

Page 58

Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY ...

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