XC4VFX40-12FFG1152C Xilinx Inc, XC4VFX40-12FFG1152C Datasheet - Page 144

• Manufacturer Part Number: XC4VFX40-12FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-12FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
Table 4-8: Block RAM Timing Parameters
144
Notes:
1. While EN is active, ADDR inputs must be stable during the entire setup/hold time window, even if WEN is inactive. Violating this
Setup and Hold Relative to Clock (CLK)
Sequential Delays
T
T
RCKO_DO
RCKO_DO
T
T
T
T
requirement can result in block RAM data corruption. If ADDR timing could violate the specified requirements, EN must be
inactive (disabled).
T
T
Parameter
RCCK_REGCE
RCKC_REGCE
T
T
RCCK_ADDR
RCKC_ADDR
T
T
T
T
RCCK_WEN
RCKC_WEN
RCCK_SSR
RCKC_SSR
RCCK_EN
RCKC_EN
RDCK_DI
RCKD_DI
Block RAM Timing Parameters
(Max)
(Min)
T
RxCK_x
Optional Output
Clock to Output
Clock to Output
Register Enable
Address inputs
Synchronous
Write Enable
Data inputs
Function
Set/Reset
Table 4-8
Enable
= Setup time (before clock edge) and T
shows the Virtex-4 FPGA block RAM timing parameters.
Control
REGCE
CLK to
CLK to
Signal
ADDR
WEN
SSR
DO
DO
EN
DI
Time before the clock that address signals must be stable at the
ADDR inputs of the block RAM.
Time after the clock that address signals must be stable at the ADDR
inputs of the block RAM.
Time before the clock that data must be stable at the DI inputs of the
block RAM.
Time after the clock that data must be stable at the DI inputs of the
block RAM.
Time before the clock that the enable signal must be stable at the EN
input of the block RAM.
Time after the clock that the enable signal must be stable at the EN
input of the block RAM.
Time before the clock that the synchronous set/reset signal must be
stable at the SSR input of the block RAM.
Time after the clock that the synchronous set/reset signal must be
stable at the SSR input of the block RAM.
Time before the clock that the write enable signal must be stable at
the WEN input of the block RAM.
Time after the clock that the write enable signal must be stable at the
WEN input of the block RAM.
Time before the clock that the register enable signal must be stable at
the REGCE input of the block RAM.
Time after the clock that the register enable signal must be stable at
the REGCE input of the block RAM.
Time after the clock that the output data is stable at the DO outputs
of the block RAM (without output register).
Time after the clock that the output data is stable at the DO outputs
of the block RAM (with output register).
www.xilinx.com
RCKx_x
= Hold time (after clock edge)
(1)
Description
(1)
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R