XC4VFX40-12FFG1152C Xilinx Inc, XC4VFX40-12FFG1152C Datasheet - Page 95

• Manufacturer Part Number: XC4VFX40-12FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-12FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
PSINCDEC
PSDONE
PSCLK
CLKIN
PSEN
CLK0
Fixed-Phase Shifting
Variable-Phase Shifting
R
D.C.
In
in phase with the desired clock phase. The clock outputs are phase-shifted to appear
sometime later than the input clock, and the LOCKED signal is asserted.
•
In
adjustments in the synchronous user interface. The PSDONE signal is asserted for one
cycle when the DCM completes one phase adjustment. After PSDONE is deasserted, PSEN
can be asserted again, allowing an additional phase shift to occur.
As shown in
synchronous to the rising edge of PSCLK.
1
Figure
Figure
Clock Event 1
Clock event 1 appears after the desired phase shifts are applied to the DCM. In this
example, the shifts are positive shifts. CLK0 and CLK2X are no longer aligned to
CLKIN. However, CLK0, and CLK2X are aligned to each other, while CLK90 and
CLK180 remain as 90° and 180° versions of CLK0. The LOCK signal is also asserted
once the clock outputs are ready.
T
T
Figure 2-22: Phase Shift Example: Variable
2-21, the DCM outputs the correct frequency. However, the clock outputs are not
DMCCK_PSEN
DMCCK_PSINCDEC
2-22, the CLK0 output is phase-shifted using the dynamic phase-shift
Figure
LOCKED
CLK180
CLK2X
CLK90
CLKIN
CLK0
2-22, all the variable-phase shift control and status signals are
Figure 2-21: Phase Shift Example: Fixed
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Lock Time
1
D.C.
2
T
DMCKO_PSDONE
ug070_2_20_083105
DCM Timing Models
ug070_2_21_071504
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