XC4VFX40-12FFG1152C Xilinx Inc, XC4VFX40-12FFG1152C Datasheet - Page 181

• Manufacturer Part Number: XC4VFX40-12FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-12FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Block RAM ECC Verilog Template
RAMB32_S64_ECC Verilog:
// RAMB32_S64_ECC: To incorporate this function into the design,
//
//
//
//
//
//
//
RAMB32_S64_ECC_inst: RAMB32_S64_ECC_inst (
generic map (
-- End of RAMB32_S64_ECC_inst instantiation
// RAMB32_S64_ECC: Virtex-4 512 x 64 Error Correction Block RAM
// Virtex-4 FPGA User Guide
RAMB32_S64_ECC #(
);
// End of RAMB32_S64_ECC_inst instantiation
declaration
<-----Cut code below this line---->
) RAMB32_S64_ECC_inst (
instance
Verilog
DO_REG => 0, -- Optional output registers (0 or 1)
port map (
);
.DO_REG(0),
.DO(DO),
.STATUS(STATUS), // 2-bit status output
.DI(DI),
.RDADDR(RDADDR), // 9-bit data address input
.RDCLK(RDCLK),
.RDEN(RDEN),
.SSR(SSR),
.WRADDR(WRADDR), // 9-bit write address input
.WRCLK(WRCLK),
.WREN(WREN)
code
DO => DO,
STATUS => STATUS, -- 2-bit status output
DI => DI,
RDADDR => RDADDR, -- 9-bit data address input
RDCLK => RDCLK,
RDEN => RDEN,
SSR => SSR,
WRADDR =>WRADDR,
WRCLK => WRCLK,
WREN => WREN
: the following instance declaration needs to be placed
: in the body of the design code. The instance name
: (RAMB32_S64_ECC_inst) and/or the port declarations
: within the parenthesis can be changed to properly
: reference and connect this function to the design.
: All inputs and outputs must be connected.
www.xilinx.com
// Optional output registers (0 or 1)
// 64-bit output data
// 64-bit data input
// 1-bit read clock input
// 1-bit read enable input
// 1-bit synchronous reset
// 1-bit write clock input
// 1-bit write enable input
-- 64-bit output data
-- 64-bit data input
-- 1-bit read clock input
-- 1-bit read enable input
-- 1-bit synchronous reset
-- 9-bit write address input
-- 1-bit write clock input
-- 1-bit write enable input
Built-in Block RAM Error Correction Code
181