XC4VFX40-12FFG1152C Xilinx Inc, XC4VFX40-12FFG1152C Datasheet - Page 362

• Manufacturer Part Number: XC4VFX40-12FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-12FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
362
Figure 7-28
Clock Event 1
•
•
Clock Event 2
•
Figure 7-29
in opposite edge mode. For other modes add the appropriate latencies as shown in
Figure 7-7, page
CE
SR
TQ
T1
C
At time T
High at the TCE input of the 3-state register, enabling the 3-state register for incoming
data.
At time T
input of the 3-state register, returning the pad to high-impedance at time T
Clock Event 1.
At time T
in this case) becomes valid-High, resetting the 3-state register at time T
Event 2.
T
OCKQ
illustrates the OLOGIC 3-state register timing.
Figure 7-28: OLOGIC 3-State Register Timing Characteristics
illustrates IOB DDR 3-state register timing. This example is shown using DDR
OTCECK
OTCK
OSRCK
326.
1
before Clock Event 1 the 3-state signal becomes valid-High at the T
before Clock Event 2, the SR signal (configured as synchronous reset
before Clock Event 1, the 3-state clock enable signal becomes valid-
T
T
OTCK
OTCECK
www.xilinx.com
2
T
OSRCK
T
RQ
3
UG070 (v2.6) December 1, 2008
4
Virtex-4 FPGA User Guide
RQ
UG070_7_28_080204
5
after Clock
OCKQ
after
R