XC4VFX40-12FFG1152C Xilinx Inc, XC4VFX40-12FFG1152C Datasheet - Page 42

• Manufacturer Part Number: XC4VFX40-12FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-12FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Clock Resources
42
BUFR Primitive
BUFR Attributes and Modes
Unlike BUFIOs, BUFRs can drive the I/O logic and logic resources (CLB, block RAM, etc.)
in the existing and adjacent clock regions. BUFRs can be driven by either the output from
BUFIOs or local interconnect. In addition, BUFR is capable of generating divided clock
outputs with respect to the clock input. The divide values are an integer between one and
eight. BUFRs are ideal for source-synchronous applications requiring clock domain
crossing or serial-to-parallel conversion. There are two BUFRs in a typical clock region
(two regional clock networks). The center column does not have BUFRs.
BUFR is a clock-in/clock-out buffer with the capability to divide the input clock frequency.
Table 1-8: BUFR Port List and Definitions
Additional Notes on the CE Pin
When CE is asserted/deasserted, the output clock signal turns on/off four input clock
cycles later. When global set/reset (GSR) signal is High, BUFR does not toggle, even if CE
is held High. The BUFR output toggles four clock cycles after the GSR signal is deasserted.
Clock division in the BUFR is controlled in software through the BUFR_DIVIDE attribute.
Table 1-9
Table 1-9: BUFR_DIVIDE Attribute
Notes:
1. Location constraint is available for BUFR.
O
CE
CLR
I
BUFR_DIVIDE
Port Name
Attribute Name
lists the possible values when using the BUFR_DIVIDE attribute.
Output
Input
Input
Input
Defines whether the output clock is a divided
version of the input clock.
Type
www.xilinx.com
CLR
Figure 1-20: BUFR Primitive
CE
I
1
1
1
1
Description
Width
ug070_1_20_071204
Clock output port
Clock enable port. Cannot be used in
BYPASS mode.
Asynchronous clear for the divide
logic, and sets the output Low. Cannot
be used in BYPASS mode.
Clock input port
O
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Definition
1, 2, 3, 4, 5, 6, 7, 8
BYPASS (default)
Possible Values
R