XC4VFX40-12FFG1152C Xilinx Inc, XC4VFX40-12FFG1152C Datasheet - Page 403

• Manufacturer Part Number: XC4VFX40-12FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-12FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Index
A
asynchronous
B
Bitslip
block RAM
BLVDS
BUFG
BUFGCE
BUFGCTRL
BUFGMUX
BUFGMUX_VIRTEX4
BUFIO
BUFR
C
Cascading DCMs
CLB
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
clocking
distributed RAM
FIFO
global set/reset
mux
set/reset in register or latch
See ISERDES
guidelines for use
operation
timing
defined
asynchronous clocking
ECC
Error Status
FIFO
operating modes
ports
synchronous clocking
with CE
array size by device
distributed RAM
maximum distributed RAM
number of flip-flops
183
41
31
383
40
297
Primitive
NO_CHANGE
READ_FIRST
WRITE_FIRST
31
36
178
116
122
124
116
384
115
33
28
37
119
,
383
122
180
366
74
,
179
147
126
189
35
188
384
119
118
119
184
184
120
119
188
184
CLK2X
CLKDV
CLKFB
CLKFX
clock capable I/O
clock forwarding
clock regions
clock tree
clocking wizard
clocks
combinatorial input path
configuration
CSE differential
D
DCI
DCLK
DCM
number of LUTs by device
number of slices by device
register/latch configuration
slice description
SLICEL
SLICEM
global clock buffers
I/O clock buffer
regional clock buffers
regions
resources
DCM
HSTL Class II
HSTL Class II (1.8V)
LVPECL
SSTL Class II (1.8V)
SSTL2 Class II (2.5V)
defined
allocation in device
attributes
clock deskew
clocking wizard
configuration
DCM to PMCD
DCM_ADV
DCM_BASE
DCM_PS
design guidelines
deskew
236
55
60
62
59
63
63
38
72
236
www.xilinx.com
38
183
74
39
183
297
58
29
65
263
89
58
356
58
40
55
72
268
105
,
89
184
40
70
70
57
25
291
323
276
285
39
,
27
,
41
184
184
188
DCMs
DDR
delay element
DESKEW_ADJUST attribute
differential termination
diode (temperature sensing)
E
Error Correction Code (ECC)
F
FIFO
FIFO16 error condition work-arounds
G
GCLK
global clocks
GSR
165
dynamic reconfiguration
frequency synthesis
location
output ports
phase shifting
ports
timing models
cascading
IDDR
ODDR
See IDELAY
special cases
DIFF_TERM
architecture
attributes
cascading
FWFT mode
operating modes
ports
primitive
standard mode
status flags
timing parameters
clock buffers
clock I/O inputs
defined
147
38
59
150
323
126
352
56
149
153
74
164
151
149
331
151
62
74
251
25
55
94
151
,
,
26
151
294
76
156
294
55
,
95
,
401
75
73
178
56
,
81
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