XC5202-6PC84C Xilinx Inc, XC5202-6PC84C Datasheet - Page 22

• Manufacturer Part Number: XC5202-6PC84C
• Description: IC FPGA 64 CLB'S 84-PLCC
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5202-6PC84C

• Number Of Logic Elements/cells: 256
• Number Of Labs/clbs: 64
• Number Of I /o: 65
• Number Of Gates: 3000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 9629
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1131

XC5200 Series Field Programmable Gate Arrays
Table 9: Pin Descriptions (Continued)
Configuration
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip.
XC5200-Series devices use several hundred bits of config-
uration data per CLB and its associated interconnects.
Each configuration bit defines the state of a static memory
cell that controls either a function look-up table bit, a multi-
plexer input, or an interconnect pass transistor. The devel-
opment system translates the design into a netlist file. It
automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Special Purpose Pins
Three configuration mode pins (M2, M1, M0) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary I/O
connections. The development system does not use these
resources unless they are explicitly specified in the design
entry. This is done by placing a special pad symbol called
MD2, MD1, or MD0 instead of the input or output pad sym-
bol.
In XC5200-Series devices, the mode pins have weak
pull-up resistors during configuration. With all three mode
pins High, Slave Serial mode is selected, which is the most
popular configuration mode. Therefore, for the most com-
mon configuration mode, the mode pins can be left uncon-
nected. (Note, however, that the internal pull-up resistor
value can be as high as 100 k .) After configuration, these
pins can individually have weak pull-up or pull-down resis-
tors, as specified in the design. A pull-down resistor value
of 3.3k
These pins are located in the lower left chip corner and are
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.
Configuration Modes
XC5200 devices have seven configuration modes. These
modes are selected by a 3-bit input code applied to the M2,
7-104
Unrestricted User-Programmable I/O Pins
Pin Name
I/O
operation
is recommended.
Config.
During
Pull-up
Weak
I/O
of
Product Obsolete or Under Obsolescence
the
Config.
After
I/O
I/O
internal
These pins can be configured to be input and/or output after configuration is completed.
Before configuration is completed, these pins have an internal high-value pull-up resis-
tor (20 k
blocks
- 100 k ) that defines the logic level as High.
and
their
M1, and M0 inputs. There are three self-loading Master
modes, two Peripheral modes, and a Serial Slave mode,
Table 10: Configuration Modes
Note :*Peripheral Synchronous can be considered byte-wide
Slave Parallel
which is used primarily for daisy-chained devices. The sev-
enth mode, called Express mode, is an additional slave
mode that allows high-speed parallel configuration. The
coding for mode selection is shown in
Note that the smallest package, VQ64, only supports the
Master Serial, Slave Serial, and Express modes.A detailed
description of each configuration mode, with timing infor-
mation, is included later in this data sheet. During configu-
ration, some of the I/O pins are used temporarily for the
configuration process.
are shown in
Master Modes
The three Master modes use an internal oscillator to gener-
ate a Configuration Clock (CCLK) for driving potential slave
devices. They also generate address and timing for exter-
nal PROM(s) containing the configuration data.
Master Parallel (Up or Down) modes generate the CCLK
signal and PROM addresses and receive byte parallel
data.
data-frame format. The up and down selection generates
starting addresses at either zero or 3FFFF, for compatibility
with different microprocessor addressing conventions. The
Master Serial
Slave Serial
Master
Parallel Up
Master
Parallel Down
Peripheral
Synchronous*
Peripheral
Asynchronous
Express
Reserved
Mode
Pin Description
The data is internally serialized into the FPGA
Table 13 on page
M2
0
1
1
1
0
1
0
0
M1
0
1
0
1
1
0
1
0
All pins used during configuration
November 5, 1998 (Version 5.2)
M0
0
1
0
0
1
1
0
1
124.
CCLK
output
output
output
output
input
input
input
—
Table
10.
from 3FFFF
from 00000
Byte-Wide,
Byte-Wide,
decrement
Byte-Wide
Byte-Wide
Byte-Wide
increment
Bit-Serial
Bit-Serial
Data
—
R