XC5202-6PC84C Xilinx Inc, XC5202-6PC84C Datasheet - Page 40

• Manufacturer Part Number: XC5202-6PC84C
• Description: IC FPGA 64 CLB'S 84-PLCC
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5202-6PC84C

• Number Of Logic Elements/cells: 256
• Number Of Labs/clbs: 64
• Number Of I /o: 65
• Number Of Gates: 3000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 9629
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1131

XC5200 Series Field Programmable Gate Arrays
Express Mode
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the con-
figuration data shift registers. A CCLK frequency of 10
MHz is equivalent to an 80 MHz serial rate, because eight
bits of configuration data are loaded per CCLK cycle.
Express mode does not support CRC error checking, but
does support constant-field error checking.
In Express mode, an external signal drives the CCLK input
of the FPGA device. The first byte of parallel configuration
data must be available at the D inputs of the FPGA a short
setup time before the second rising CCLK edge. Subse-
quent data bytes are clocked in on each consecutive rising
CCLK edge.
If the first device is configured in Express mode, additional
devices may be daisy-chained only if every device in the
chain is also configured in Express mode. CCLK pins are
tied together and D0-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. The
lead device in the chain has its CS1 input tied High (or float-
ing, since there is an internal pullup).
accepted only when CS1 is High and the device’s configu-
7-122
Figure 37: Express Mode Circuit Diagram
DATA BUS
PROGRAM
CCLK
INIT
8
4.7K
Product Obsolete or Under Obsolescence
VCC
PROGRAM
CS1
D0-D7
INIT
CCLK
M0
XC5200
M1
Frame data is
DOUT
M2
DONE
8
ration memory is not already full. The status pin DOUT is
pulled Low two internal-oscillator cycles after INIT is recog-
nized as High, and remains Low until the device’s configu-
ration memory is full. DOUT is then pulled High to signal
the next device in the chain to accept the configuration data
on the D0-D7 bus.
The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a
large number of devices are included in the chain, deacti-
vate some of the internal pull-ups, since the Low-driving
DONE pin of the last device in the chain must sink the cur-
rent from all pull-ups in the chain. The DONE pull-up is
activated by default. It can be deactivated using an option
in the bitstream generation software.
XC5200 devices in Express mode are always synchronized
to DONE. The device becomes active after DONE goes
High. DONE is an open-drain output. With the DONE pins
tied together, therefore, the external DONE signal stays low
until all devices are configured, then all devices in the daisy
chain become active simultaneously. If the DONE pin of a
device is left unconnected, the device becomes active as
soon as that device has been configured.
Express mode is selected by a <010> on the mode pins
(M2, M1, M0).
8
PROGRAM
CS1
D0-D7
INIT
CCLK
M0
Daisy-Chained
Optional
XC5200
M1
DOUT
DONE
M2
3.3 k
VCC
November 5, 1998 (Version 5.2)
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
To Additional
Optional
Daisy-Chained
Devices
To Additional
Optional
Daisy-Chained
Devices
X6611_01
R