XC5202-6PC84C Xilinx Inc, XC5202-6PC84C Datasheet - Page 32

• Manufacturer Part Number: XC5202-6PC84C
• Description: IC FPGA 64 CLB'S 84-PLCC
• Manufacturer: Xilinx Inc
• Series: XC5200r

Specifications of XC5202-6PC84C

• Number Of Logic Elements/cells: 256
• Number Of Labs/clbs: 64
• Number Of I /o: 65
• Number Of Gates: 3000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 9629
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Other names: 122-1131

XC5200 Series Field Programmable Gate Arrays
Configuration Timing
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
Note:
Figure 29: Slave Serial Mode Programming Switching Characteristics
7-114
Figure 28: Master/Slave Serial Mode Circuit Diagram
CCLK
Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
PROGRAM
(Output)
DOUT
3.3 K
CCLK
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
DIN
3.3 K
DIN setup
DIN hold
DIN to DOUT
High time
Low time
Frequency
M2
PROGRAM
DONE
Product Obsolete or Under Obsolescence
M0 M1
MASTER
SERIAL
XC5200
3.3 K
Description
DOUT
CCLK
LDC
INIT
1 T
DIN
DCC
Bit n
VCC
4.7 K
2 T
(Low Reset Option Used)
CCD
CLK
CE
DATA
RESET/OE
XC1700E
Bit n - 1
4 T
1
2
3
4
5
CCH
CEO
VPP
Symbol
+5 V
T
T
T
T
T
F
N/C
DCC
CCD
CCO
CCH
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
Figure 28
XC5200-Series device in Slave Serial mode should be con-
nected as shown in the third device from the left.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
tors during configuration.
CCL
CC
Bit n + 1
DIN
CCLK
PROGRAM
M2
DONE
M0 M1
N/C
XC4000E/EX,
Spartan,
XC5200
SLAVE
3 T
shows
DOUT
Min
CCO
20
45
45
INIT
0
5 T
CCL
a
3.3 K
VCC
full
November 5, 1998 (Version 5.2)
3.3 K
NOTE:
M2, M1, M0 can be shorted
to VCC if not used as I/O
master/slave
Max
M2
CCLK
RESET
D/P
DIN
30
10
M0
Bit n
M1 PWRDN
XC3100A
SLAVE
3.3 K
DOUT
INIT
X5379
X9003_01
system.
Units
MHz
ns
ns
ns
ns
ns
An
R