AT94K05AL-25BQU Atmel, AT94K05AL-25BQU Datasheet - Page 105

• Manufacturer Part Number: AT94K05AL-25BQU
• Description: IC FPSLIC 5K GATE 25MHZ 144-LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25BQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.26.1
4.26.2
1138I–FPSLI–1/08
TCNT1 Timer/Counter1 Write
TCNT1 Timer/Counter1 Read
Table 4-19.
The Stop condition provides a Timer Enable/Disable function. The CK down-divided modes are
scaled directly from the CK oscillator clock. If the external pin modes are used for
Timer/Counter1, transitions on PE4/(T1) will clock the counter even if the pin is configured as an
output. This feature can give the user SW control of the counting.
Timer/Counter1 Register – TCNT1H AND TCNT1L
This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that
both the High and low bytes are read and written simultaneously when the CPU accesses these
registers, the access is performed using an 8-bit temporary register (TEMP). This temporary reg-
ister is also used when accessing OCR1A, OCR1B and ICR1. If the main program and also
interrupt routines perform access to registers using TEMP, interrupts must be disabled during
access from the main program and interrupt routines.
When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP register.
Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte
data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 register
simultaneously. Consequently, the high byte TCNT1H must be accessed first for a full 16-bit reg-
ister write operation.
When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU
and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU reads the
data in the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently,
the low byte TCNT1L must be accessed first for a full 16-bit register read operation.
Bit
$2D ($4D)
$2C ($4C)
Read/Write
Initial Value
CS12
0
0
0
0
1
1
1
1
Clock 1 Prescale Select
15
MSB
7
R/W
R/W
0
0
CS11
0
0
1
1
0
0
1
1
14
6
R/W
R/W
0
0
CS10
0
1
0
1
0
1
0
1
13
5
R/W
0
0
R/W
Description
Stop, the Timer/Counter1 is stopped
CK
CK/8
CK/64
CK/256
CK/1024
External pin PE4 (T1), falling edge
External pin PE4 (T1), rising edge
12
4
R/W
R/W
0
0
AT94KAL Series FPSLIC
11
3
R/W
R/W
0
0
10
2
R/W
R/W
0
0
9
1
R/W
R/W
0
0
8
LSB
0
R/W
R/W
0
0
TCNT1H
TCNT1L
105