AT94K05AL-25BQU Atmel, AT94K05AL-25BQU Datasheet - Page 40

• Manufacturer Part Number: AT94K05AL-25BQU
• Description: IC FPSLIC 5K GATE 25MHZ 144-LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25BQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 4-2.
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
40
Mnemonics
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
BREAK
Pin Descriptions
AT94KAL Series FPSLIC
V
GND
PortD (PD7..PD0)
PortE (PE7..PE0)
RX0
TX0
CC
Instruction Set Summary (Continued)
Operands
Supply voltage
Ground
Port D is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port D
output buffers can be programmed to sink/source either 6 or 20 mA (SCR54 – see
trol Register – FPGA/AVR” on page
source current if the programmable pull-up resistors are activated.
The Port D pins are input with pull-up when a reset condition becomes active, even if the clock is
not running. On lower pin count packages Port D may not be available. Check the Pin List for
details.
Port E is an 8-bit bi-directional I/O port with internal programmable pull-up resistors. The Port E
output buffers can be programmed to sink/source either 6 or 20 mA (SCR55 – see
trol Register – FPGA/AVR” on page
source current if the pull-up resistors are activated.
Port E also serves the functions of various special features. See
The Port E pins are input with pull-up when a reset condition becomes active, even if the clock is
not running
Input (receive) to UART(0) – See SCR52
Output (transmit) from UART(0) – See SCR52
Description
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half-carry Flag in SREG
Clear Half-carry Flag in SREG
No Operation
Sleep
Watchdog Reset
Break
30). As inputs, Port D pins that are externally pulled Low will
30). As inputs, Port E pins that are externally pulled Low will
Operation
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
(See specific description for Sleep)
(See specific description for WDR)
For on-chip debug only
Table 4-35 on page
Flags
V
V
T
T
H
H
None
None
None
None
“System Con-
“System Con-
1138I–FPSLI–1/08
160.
#Clock
1
1
1
1
1
1
1
1
1
N/A