AT94K05AL-25BQU Atmel, AT94K05AL-25BQU Datasheet - Page 65

• Manufacturer Part Number: AT94K05AL-25BQU
• Description: IC FPSLIC 5K GATE 25MHZ 144-LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25BQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.16.3
4.16.4
4.16.5
4.16.6
1138I–FPSLI–1/08
External Reset
Watchdog Reset
Software Reset
Interrupt Handling
The MCU after five CPU clock-cycles, and can be used when an external clock signal is applied
to the XTAL1 pin. This setting does not use the WDT oscillator, and enables very fast start-up
from the Sleep, Power-down or Power-save modes if the clock signal is present during sleep.
RESET can be connected to V
Low for a period after V
to
Figure 4-15. MCU Start-up, RESET Controlled Externally
An external reset is generated by a low-level on the AVRRESET pin. When the applied signal
reaches the Reset Threshold Voltage – V
MCU after the Time-out period t
When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
period t
dependent.
See
The embedded AVR core has one dedicated 8-bit Interrupt Mask control register: TIMSK –
Timer/Counter Interrupt Mask Register. In addition, other enable and mask bits can be found in
the peripheral control registers.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are
disabled. The user software can set (one) the I-bit to enable nested interrupts. The I-bit is set
(one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute the
interrupt handling routine, the hardware clears the corresponding flag that generated the inter-
rupt. Some of the interrupt flags can also be cleared by writing a logic 1 to the flag bit position(s)
to be cleared.
Figure 4-15
INTERNAL RESET
“Software Control of System Configuration” on page
TOUT
TIME-OUT
is approximately 3 µs – at V
for a timing example on this.
RESET
V
CC
CC
has been applied, the Power-on Reset period can be extended. Refer
CC
TOUT
directly or via an external pull-up resistor. By holding the pin
V
has expired.
POT
RST
CC
– on its positive edge, the delay timer starts the
= 3.3V. the period of the time out is voltage
AT94KAL Series FPSLIC
V
RST
t
TOUT
52.
TOUT
. Time-out
65