AT94K05AL-25BQU Atmel, AT94K05AL-25BQU Datasheet - Page 147

• Manufacturer Part Number: AT94K05AL-25BQU
• Description: IC FPSLIC 5K GATE 25MHZ 144-LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25BQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.30.1.4
1138I–FPSLI–1/08
Slave Transmitter Mode
TWEN must be set to enable the 2-wire Serial Interface. The TWEA bit must be set to enable the
acknowledgment of the device’s own Slave address or the general call address. TWSTA and
TWSTO must be cleared.
When TWAR and TWCR have been initialized, the 2-wire Serial Interface waits until it is
addressed by its own Slave address (or the general call address if enabled) followed by the data
direction bit which must be “0” (write) for the 2-wire Serial Interface to operate in the Slave
Receiver mode. After its own Slave address and the write bit have been received, the 2-wire
Serial Interrupt flag is set and a valid status code can be read from TWSR. The status code is
used to determine the appropriate software action. The appropriate action to be taken for each
status code is detailed in
tion is lost while the 2-wire Serial Interface is in the Master mode (see states $68 and $78).
If the TWEA bit is reset during a transfer, the 2-wire Serial Interface will return a “Not Acknowl-
edged” (1) to SDA after the next received data byte. While TWEA is reset, the 2-wire Serial
Interface does not respond to its own Slave address. However, the 2-wire Serial Bus is still mon-
itored and address recognition may resume at any time by setting TWEA. This implies that the
TWEA bit may be used to temporarily isolate the 2-wire Serial Interface from the 2-wire serial
bus.
In ADC Noise Reduction Mode, Power-down Mode and Power-save Mode, the clock system to
the 2-wire Serial Interface is turned off. If the Slave Receiver mode is enabled, the interface can
still acknowledge a general call and its own Slave address by using the 2-wire serial bus clock
as a clock source. The part will then wake up from sleep and the 2-wire Serial Interface will hold
the SCL clock Low during the wake up and until the TWCINT flag is cleared.
Note that the 2-wire Serial Data Register – TWDR does not reflect the last byte present on the
bus when waking up from these Sleep Modes.
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver
(see
TWCR have been initialized, the 2-wire Serial Interface waits until it is addressed by its own
Slave address (or the general call address if enabled) followed by the data direction bit which
must be “1” (read) for the 2-wire Serial Interface to operate in the Slave Transmitter mode. After
its own Slave address and the read bit have been received, the 2-wire Serial Interrupt flag is set
and a valid status code can be read from TWSR. The status code is used to determine the
appropriate software action. The appropriate action to be taken for each status code is detailed
in
wire Serial Interface is in the Master mode (see state $B0).
If the TWEA bit is reset during a transfer, the 2-wire Serial Interface will transmit the last byte of
the transfer and enter state $C0 or state $C8. the 2-wire Serial Interface is switched to the not
addressed Slave mode, and will ignore the Master if it continues the transfer. Thus the Master
Receiver receives all “1” as serial data. While TWEA is reset, the 2-wire Serial Interface does not
respond to its own Slave address. However, the 2-wire serial bus is still monitored and address
recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be
used to temporarily isolate the 2-wire Serial Interface from the 2-wire serial bus.
Table
Figure
4-32. The Slave Transmitter mode may also be entered if arbitration is lost while the 2-
4-51). The transfer is initialized as in the Slave Receiver mode. When TWAR and
Table
4-31. The Slave Receiver mode may also be entered if arbitra-
AT94KAL Series FPSLIC
147