AT94K05AL-25BQU Atmel, AT94K05AL-25BQU Datasheet - Page 120

• Manufacturer Part Number: AT94K05AL-25BQU
• Description: IC FPSLIC 5K GATE 25MHZ 144-LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25BQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.28.6.1
4.28.6.2
120
AT94KAL Series FPSLIC
Example 5 – Basic Usage 8-bit x 8-bit = 16-bit Signed Fractional Multiply
Example 6 – Multiply-accumulate Operation
Since we do not have a rest, the remaining three bits will be zero, and the final result is “1110
1000”, which is 1 + 0.5 + 0.25 + 0.0625 = 1.8125.
To convert a negative fractional number, first add 2 to the number and then use the same algo-
rithm as already shown.
16-bit fractional numbers use a format similar to that of 8-bit fractional numbers; the high 8 bits
have the same format as the 8-bit format. The low 8 bits are only an increase of accuracy of the
8-bit format; while the 8-bit format has an accuracy of ± 2
± 2
16-bit fractional numbers. Note the important difference between integers and fractional num-
bers when extra byte(s) are used to store the number: while the accuracy of the numbers is
increased when fractional numbers are used, the range of numbers that may be represented is
extended when integers are used.
As mentioned earlier, using signed fractional numbers in the range [-1, 1> has one main advan-
tage to integers: when multiplying two numbers in the range [-1, 1>, the result will be in the
range [-1, 1], and an approximation (the highest byte(s)) of the result may be stored in the same
number of bytes as the factors, with one exception: when both factors are -1, the product should
be 1, but since the number 1 cannot be represented using this number format, the FMULS
instruction will instead place the number -1 in R1:R0. The user should therefore assure that at
least one of the operands is not -1 when using the FMULS instruction. The
16-bit x 16-bit fractional multiply also has this restriction.
This example shows an assembly code that reads the port E input value and multiplies this
value with a fractional constant (-0.625) before storing the result in register pair R17:R16.
Note that the usage of the FMULS (and FMUL) instructions is very similar to the usage of the
MULS and MUL instructions.
The example below uses data from the ADC. The ADC should be configured so that the format
of the ADC result is compatible with the fractional two’s complement format. For the
ATmega83/163, this means that the ADLAR bit in the ADMUX I/O register is set and a differen-
tial channel is used. The ADC result is normalized to one.
-16
in
ldi
fmulsr16,r17
movw r17:r16,r1:r0 ; Move the result to the r17:r16
ldi r23,$62
ldi r22,$C0
in r20,ADCL
in r21,ADCH
callfmac16x16_32 ;Call routine for signed fractional
. Then again, the 32-bit fractional numbers are an increase of accuracy to the
r16,PINE
r17,$B0
; Load highbyte of
; fraction 0.771484375
; Load lowbyte of
; fraction 0.771484375
; Get lowbyte of ADC conversion
; Get highbyte of ADC conversion
; multiply accumulate
; Read pin values
; Load -0.625 into r17
; r1:r0 = r17 * r16
; register pair
-8
, the16-bit format has an accuracy of
1138I–FPSLI–1/08