AT94K05AL-25BQU Atmel, AT94K05AL-25BQU Datasheet - Page 70

• Manufacturer Part Number: AT94K05AL-25BQU
• Description: IC FPSLIC 5K GATE 25MHZ 144-LQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K05AL-25BQU

• Core Type: 8-bit AVR
• Speed: 25MHz
• Interface: I²C, UART
• Program Sram Bytes: 4K-16K
• Fpga Sram: 2kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 256
• Fpga Gates: 5K
• Fpga Registers: 436
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same time-set bits that define the
reset time-out period. The wake-up period is equal to the clock reset period, as shown in
Figure 1 on page
93.
If the wake-up condition disappears before the MCU wakes up and starts to execute, the inter-
rupt causing the wake-up will not be executed.
4.17.3
Power-save Mode
When the SM1/SM0 bits are 11, the SLEEP instruction makes the MCU enter the Power-save
mode. This mode is identical to power-down, with one exception:
If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2
will run during sleep. In addition to the power-down wake-up sources, the device can also wake-
up from either Timer Overflow or Output Compare event from Timer/Counter2 if the correspond-
ing Timer/Counter2 interrupt enable bits are set in TIMSK. To ensure that the part executes the
Interrupt routine when waking up, also set the global interrupt enable bit in SREG.
When waking up from Power-save mode by an external interrupt, two instruction cycles are exe-
cuted before the interrupt flags are updated. When waking up by the asynchronous timer, three
instruction cycles are executed before the flags are updated. During these cycles, the processor
executes instructions, but the interrupt condition is not readable, and the interrupt routine has
not started yet. See
Table 2-1 on page 15
for clock activity during Power-down, Power-save and
Idle modes.
AT94KAL Series FPSLIC
70
1138I–FPSLI–1/08