CY7C64713-56LFXC Cypress Semiconductor Corp, CY7C64713-56LFXC Datasheet - Page 18

• Manufacturer Part Number: CY7C64713-56LFXC
• Description: IC MCU USB EZ FX1 16KB 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-56LFXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1680; CY7C64713-56LFXC

Table 8. FX1 Pin Definitions (continued)
Document #: 38-08039 Rev. *F
TQFP
Port A
128
99
35
12
11
82
83
84
85
89
90
1
TQFP
100
100
77
10
67
68
69
70
71
72
11
SSOP
56
49
12
40
41
42
43
44
45
11
5
QFN
56
42
54
33
34
35
36
37
38
5
4
RESET#
EA
XTALIN
XTALOUT
CLKOUT
PA0 or
INT0#
PA1 or
INT1#
PA2 or
SLOE
PA3 or
WU2
PA4 or
FIFOADR0
PA5 or
FIFOADR1
Name
Type
Input
Input
Input
Output
O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Default
(PA0)
(PA1)
(PA2)
(PA3)
(PA4)
(PA5)
MHz
N/A
N/A
N/A
N/A
12
I
I
I
I
I
I
Active LOW Reset. Resets the entire chip. See the section
Wakeup”
External Access. This pin determines where the 8051 fetches code
between addresses 0x0000 and 0x3FFF. If EA = 0 the 8051 fetches
this code from its internal RAM. IF EA = 1 the 8051 fetches this code
from external memory.
Crystal Input. Connect this signal to a 24 MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
It is also correct to drive the XTALIN with an external 24 MHz square
wave derived from another clock source. When driving from an external
source, the driving signal must be a 3.3V square wave.
Crystal Output. Connect this signal to a 24 MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
CLKOUT: 12, 24 or 48 MHz clock, phase locked to the 24 MHz input
clock. The 8051 defaults to 12 MHz operation. The 8051 may
three-state this output by setting CPUCS.1 = 1.
Multiplexed pin whose function is selected by PORTACFG.0
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional I/O port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit
(WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is
in suspend and WU2EN = 1, a transition on this pin starts up the oscil-
lator and interrupts the 8051 to allow it to exit the suspend mode.
Asserting this pin inhibits the chip from suspending, if WU2EN = 1.
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
on page 6 for more details.
Description
CY7C64713
Page 18 of 55
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