CY7C64713-56LFXC Cypress Semiconductor Corp, CY7C64713-56LFXC Datasheet - Page 33

• Manufacturer Part Number: CY7C64713-56LFXC
• Description: IC MCU USB EZ FX1 16KB 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-56LFXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1680; CY7C64713-56LFXC

Table 12. Data Memory Read Parameters
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is active only when either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
Document #: 38-08039 Rev. *F
Note
t
t
t
t
t
t
t
t
14. t
CL
AV
STBL
STBH
SCSL
SOEL
DSU
DH
Parameter
t
t
t
t
ACC2
ACC2
ACC2
ACC3
ACC3
(24 MHz) = 3*t
(48 MHz) = 3*t
(24 MHz) = 5*t
(48 MHz) = 5*t
and t
ACC3
CLKOUT
CLKOUT
are computed from the parameters in
1/CLKOUT Frequency
Delay from Clock to Valid Address
Clock to RD LOW
Clock to RD HIGH
Clock to CS LOW
Clock to OE LOW
Data Setup to Clock
Data Hold Time
CL
CL
CL
CL
– t
– t
– t
– t
A[15..0]
A[15..0]
D[7..0]
D[7..0]
[12]
AV
AV
AV
AV
[12]
OE#
RD#
RD#
CS#
CS#
– t
– t
– t
– t
DSU
DSU
DSU
DSU
= 106 ns
= 43 ns
= 190 ns
= 86 ns.
Description
t
t
AV
AV
t
t
CL
CL
Figure 13. Data Memory Read Timing Diagram
Table 12
t
STBL
t
t
ACC1
SCSL
t
SOEL
[14
as follows:
Stretch = 0
Stretch = 1
t
data in
DSU
Min
9.6
0
t
ACC1
[14]
t
STBH
t
DH
20.83
41.66
83.2
Typ
t
AV
t
data in
DSU
Max
10.7
11.1
11
11
13
t
DH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CY7C64713
48 MHz
24 MHz
12 MHz
Notes
Page 33 of 55
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