CY7C64713-56LFXC Cypress Semiconductor Corp, CY7C64713-56LFXC Datasheet - Page 42

• Manufacturer Part Number: CY7C64713-56LFXC
• Description: IC MCU USB EZ FX1 16KB 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-56LFXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1680; CY7C64713-56LFXC

Slave FIFO Asynchronous Packet End Strobe
In the following figure, dashed lines indicate signals with programmable polarity.
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz
Table 24. Slave FIFO Asynchronous Packet End Strobe Parameters
Slave FIFO Output Enable
In the following figure, dashed lines indicate signals with programmable polarity.
Table 25. Slave FIFO Output Enable Parameters
Slave FIFO Address to Flags/Data
In the following figure, dashed lines indicate signals with programmable polarity.
Table 26. Slave FIFO Address to Flags/Data Parameters
Document #: 38-08039 Rev. *F
t
t
t
t
t
t
t
PEpwl
PWpwh
XFLG
OEon
OEoff
XFLG
XFD
Parameter
Parameter
Parameter
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
PKTEND to FLAGS Output Propagation Delay
SLOE Assert to FIFO DATA Output
SLOE Deassert to FIFO DATA Hold
FIFOADR[1:0] to FLAGS Output Propagation Delay
FIFOADR[1:0] to FIFODATA Output Propagation Delay
Figure 25. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
FIFOADR [1.0]
PKTEND
DATA
Figure 27. Slave FIFO Address to Flags/Data Timing Diagram
SLOE
FLAGS
FLAGS
DATA
Figure 26. Slave FIFO Output Enable Timing Diagram
Description
Description
Description
t
PEpwl
t
XFLG
t
OEon
t
XFLG
t
XFD
N
t
N+1
PEpwh
t
OEoff
Min
50
50
14.3
Max
10.5
10.5
Max
10.7
Max
115
Unit
Unit
ns
ns
ns
ns
.
CY7C64713
Unit
ns
ns
ns
Page 42 of 55
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