PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 504
PNX1500E/G,557
Manufacturer Part Number
PNX1500E/G,557
Description
IC MEDIA PROC 240MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1500E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.14 V ~ 1.26 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1296
935277746557
PNX1500E/G
935277746557
PNX1500E/G
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Table 3: Fast general purpose INput (FGPI)
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x07,000C
31:24
23:0
Offset 0x07,0010
31:24
23:0
Offset 0x07,0014
31:2
1:0
Offset 0x07,0018
31:24
23:0
Offset 0x07,001C
31:24
23:0
Offset 0x07,0020
31:24
23:0
Offset 0x07,0024
31:24
23:0
Symbol
Reserved
SIZE
Reserved
REC_SIZE
STRIDE
Reserved
Reserved
NREC1
Reserved
NREC2
Reserved
THRESH1
Reserved
THRESH2
FGPI_SIZE
FGPI_REC_SIZE
FGPI_STRIDE
FGPI_NREC1
FGPI_NREC2
FGPI_THRESH1
FGPI_THRESH2
Acces
s
R
R/W
R
R/W
R/W
R
R
R
R
R
R
R/W
R
R/W
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
…Continued
Rev. 4.0 — 03 December 2007
Description
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of records/messages per buffer. Range: 1 to 2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of samples per record/message. Range: 2 to 2
(See
Address stride between records/messages
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of records/messages sent to buffer 1.
Cleared to zero when FGPI_BASE1 register is written to.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Number of records/messages sent to buffer 2.
Cleared to zero when FGPI_BASE2 register is written to.
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
THRESH1_REACHED interrupt generated when FGPI_NREC1
count equals this register value. Range: 1 to 2
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
THRESH2_REACHED interrupt generated when FGPI_NREC2
count equals this register value. Range: 1 to 2
Section 3.2.1 on page 14-497
Chapter 14: FGPI: Fast General Purpose Interface
PNX15xx/952x Series
on minimum REC_SIZE)
24
24
© NXP B.V. 2007. All rights reserved.
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