PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 59
PNX1500E/G,557
Manufacturer Part Number
PNX1500E/G,557
Description
IC MEDIA PROC 240MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1500E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.14 V ~ 1.26 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1296
935277746557
PNX1500E/G
935277746557
PNX1500E/G
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Table 32: Reset Timing
Table 33: DDR DRAM Interface Timing
PNX15XX_PNX952X_SER_N_4
Product data sheet
Symbol
T
T
T
Symbol
F
T
T
T
T
T
oh-dq
LOWP
HOLD
LOWR
ddr
ddr
cs
pd-cmd
s-dq
Parameter
Reset active time after power and clock stable
Reset active after POR_IN_N is pulled high
Reset active time after power and clock stable
Parameter
MM_CLK and MM_CLK_N frequency
MM_CLK and MM_CLK_N period
MM_CLK and MM_CLK_N skew
Propagation delay for command signals
Setup time for MM_DQ and MM_DQM
(when writing to DDR SDRAM)
Output hold time for MM_DQ and MM_DQM
(when writing to DDR SDRAM)
7.1 Reset
7.2 DDR DRAM Interface
[32-1]
[32-2]
[32-3]
PNX1500 supports DDR200, DDR266, DDR400{A,B,C} DDR devices as defined in
the JEDEC STANDARD JESD79C, March 2003. Refer to
interface
Figure 9:
Notes:
1. Can be asserted and de-asserted asynchronously with respect to CLK.
2. If POR_IN_N and RESET_IN_N are asserted low then RESET_IN_N must stay low for at
least as long as POR_IN_N is asserted low.
for more details.
Reset Timing
Rev. 4.0 — 03 December 2007
POR_IN_N
RESET_IN_N
T
Min
83
5
1.4
- 0.12
0.12
LOWP
Min
100
0
100
T
LOWR
PNX15xx/952x Series
Chapter 1: Integrated Circuit Data
T
HOLD
Max
Section 4.
12
0.01
3.6
Max
Section 10.3 DDR SDRAM
Units
MHz
ns
ns
ns
T
T
ddr
ddr
Units
ns
s
s
© NXP B.V. 2007. All rights reserved.
Notes
i.e. up to
DDR400
1, 2, 3, 5
4, 5
4, 5
Notes
1
2
1
1-59
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