SL11R Cypress Semiconductor Corp, SL11R Datasheet
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... SL11R USB Controller/ 16-Bit RISC Processor Data Sheet Cypress Semiconductor Corporation Document #: 38-08006 Rev. ** • 3901 North First Street • San Jose SL11R • CA 95134 • 408-943-2600 Revised December 3, 2001 ...
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... DEFINITIONS .................................................................................................................................. 8 2.0 REFERENCES ................................................................................................................................ 8 3.0 INTRODUCTION ............................................................................................................................. 8 3.1 Overview ......................................................................................................................................... 8 3.2 SL11R Features .............................................................................................................................. 8 3.3 SL11R 16-Bit RISC Processor .................................................................................................... 10 3.4 3Kx16 Mask ROM and BIOS ........................................................................................................ 10 3.5 Internal RAM ................................................................................................................................. 10 3.6 Clock Generator ........................................................................................................................... 11 3.7 USB Interface ............................................................................................................................... 11 3.8 Processor Control Registers ...................................................................................................... 11 3.9 Interrupts ...................................................................................................................................... 11 3.10 UART Interface ........................................................................................................................... 11 3.11 *2-wire Serial EEPROM Interface .............................................................................................. 11 3 ...
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... DMA Control Register (0xC02A: R/W) ............................................................................................ 37 4.18.2 Low DMA Start Address Register (0xC02C: R/W) ......................................................................... 37 4.18.3 High DMA Start Address Register (0xC02E: R/W) ......................................................................... 38 4.18.4 Low DMA Stop Address Register (0xC030: R/W) ..........................................................................38 4.18.5 High DMA Stop Address Register (0xC032: R/W) ......................................................................... 38 Document #: 38-08006 Rev. ** Table of Contents (continued) SL11R Page ...
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... GPIO and 8/16-Bit DMA Modes—Pin Assignment and Description ........................................ 49 6.3 Fast EPP Pin Assignment and Description ............................................................................... 52 6.4 DVC 8-Bit DMA Mode Pin Assignment and Description .......................................................... 54 7.0 SL11R CPU PROGRAMMING GUIDE ......................................................................................... 57 7.1 Instruction Set Overview ............................................................................................................. 57 7.2 Reset Vector ................................................................................................................................. 57 7.3 Register Set .................................................................................................................................. 57 7 ...
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... SL11R DRAM Timing ................................................................................................................. 73 8.15 SL11R DRAM Read Cycle ........................................................................................................ 74 8.16 SL11R DRAM Write Cycle ........................................................................................................ 75 8.17 SL11R CAS-Before-RAS Refresh Cycle ................................................................................... 76 8.18 SL11R DRAM Page Mode Read Cycle ..................................................................................... 77 8.19 DRAM Page Mode Write Cycle ................................................................................................. 78 8.20 SL11R SRAM Read Cycle .......................................................................................................... 79 8.21 SL11R SRAM Write Cycle ......................................................................................................... 80 8 ...
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... Figure 4-7. PWM Block Diagram ....................................................................................................... 34 Figure 5-1. GPIO Mode Block Diagram\ ........................................................................................... 40 Figure 5-2. 8/16-bit DMA Mode Block Diagram ............................................................................... 41 Table 4-1. Internal Masked ROM (SL11R BIOS) .............................................................................. 15 Table 4-2. Internal RAM Memory Usage .......................................................................................... 16 Table 4-3. Hardware Interrupt Table ................................................................................................. 24 Table 4-4. Software Interrupt Table .................................................................................................. 26 Table 4-5 ...
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... Cypress products, expressly or by implication. Cypress’s products are not authorized for use as critical components in life support devices or systems. SL11R is a trademark of the Cypress Semiconductor Corporation. All other product names are trademarks or registered trade- marks of their respective owners. Document #: 38-08006 Rev. ** ...
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... Data Port supports both DMA and I/O modes. A built in USB port supports data transfers MBits/sec which is the maximum USB transfer rate. All USB protocol modes are supported: Isochronous (up to 1024 bytes/packet), Bulk, Interrupt, and Control. The SL11R requires a 3.3-Volt power supply, which can be powered via a USB host Hub. Suspend/Resume, and Low power modes are available. ...
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... bits of General Purpose I/O (GPIO) • 6Kx8 internal Mask ROM with built-in BIOS in supporting a comprehensive list of interrupt calls (see [Ref. 1] SL11R_BIOS for detailed information). These include USB functions, 2-wire serial interface, and UART and Boot-Up options (Boot-up from 2-wire serial interface or External ROM). Executable code can also run from 8-bit or 16-bit external Memory. ...
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... Internal RAM The SL11R contains internal RAM. The RAM can be used for code/program, variables, buffer I/O, DMA data (i.e. Video data), and USB packets. This memory can be accessed by the 16-Bit processor for data manipulation or by the SIE (Serial Interface Engine), which receives or sends USB host data. ...
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... Clock Generator A 12, 48 MHz external Crystal, or logic-level clock can be used with the SL11R. Two pins, X1 and X2, are provided to connect a low cost crystal circuit to the device logic-level clock is available, it may be connected directly to the X1 pin instead of a crystal. Register C006 must be configured appropriately depending on the frequency used. ...
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... When a word is written to the SL11R, the ‘IF’ (INBUFF FULL) bit in the status register (0xC0C2) is set by the SL11R hardware. This bit must be polled until it is cleared to ‘0’ by the SL11R. This indicates that the word has been accepted by the SL11R and that it is ready for another word. When data is read from the SL11R, the ‘ ...
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... The 22-bit DMA end address register is loaded through registers 0xC030 and 0xC032. This will be location of the last word written into the SL11R. When reading data out of the SL11R, the end address register should be loaded with the last address to be read from plus two. After these registers are loaded, the DMA control register (0xC0C0) must be loaded with a 0x0007 to enable the DREQ output pin ...
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... SL11R Interface Modes The SL11R has four modes. They are: General Purpose I/O mode, Fast EPP mode, 8-bit DMA mode, and 8/16-bit DMA Mailbox Protocol ports mode. These modes are shared and can be configured under software control. Note: The UART and 2-wire serial interface I/O pins are fixed in all cases. ...
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... The SL11R 16-bit processor has direct access to the control port and the camera operation is dependent on com- mands passed from the USB Host to the SL11R. Raw video data from the CCD Camera is input to the SL11R on the 8-bit video data bus (SD7-SD0) using a combination of clock, control signals and 8-bit DMA. ...
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... Note: 2. This address may be changed due to SL11R BIOS revision updates. The new SL11R BIOS may require more internal memory for its variable usage in any new SL11R BIOS. • The addresses from 0x0000 to 0x00FF are reserved for hardware and software interrupt vectors (see [Ref. 1] SL11R_BIOS for more information). • ...
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... Note: You need to set bit C2 =1 from configuration address (0xC006). See section 4.5 for CPU control speed. Document #: 38-08006 Rev MHz, series, 20-pF load Figure 4-1. 48-MHz Crystal Circuit MHz, series, 20-pF load Figure 4-2. 12-MHz Crystal Circuit SL11R X2 Rs 100 Cout 2.7K Cout 22 pF Page ...
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... The SL11R has a built-in transceiver that meets the USB specification v1.1. The transceiver connects directly to the physical layer of the USB engine capable of transmitting or receiving serial data at the USB maximum data rate of 12 Mbits/sec. The SL11R has four USB DMA engines for four USB endpoints. Each of the USB DMA engines is independently responsible for its respective USB transaction ...
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... General Description for All Endpoints from Endpoint 0 to Endpoint 3 The SL11R Controller supports four endpoints. Endpoint 0 is the default pipe and is used to initialize and control the peripheral device. It also provides access to the peripheral device's configuration information, and supports control transfers. Endpoint 1, 2, and 3 support interrupt transfers, bulk transfers Bytes/packet, or Isochronous transfers up to 1024 Bytes/packet size ...
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... When the Zero Length bit (D5) is set, the host will receive the zero length USB packet, regardless of the number of bytes in the USB Count register. • The SL11R BIOS has full control of USB endpoint 0. The SL11R BIOS responds to all numeration from the host. On other endpoints, the SL11R BIOS can be used to control under BIOS interrupt calls (see [Ref. 1] SL11R_BIOS). ...
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... USB Endpoint 3 Count Register (0x012E: R/W) See USB Endpoint 0 Count Register (0x0122: R/W) 4.10 Processor Control Registers The SL11R provides software control registers that can be used to configure the chip mode, clock control, read software version and software breakpoint control. 4.10.1 Configuration Register (0xC006: R/W) The Configuration Register is used to configure the SL11R into the appropriate mode, and to select a clock multiplier ...
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... Speed will also depend on the clock multiplier. See Configuration Register (0xC006: R/W) for more information. D3-D0 SPD3-SPD0 D15-D4 Reserved Note: Upon reset, the lowest speed is selected for low power operation. The SL11R BIOS will configure the clock to 24MHz as part of its initialization. Document #: 38-08006 Rev. ** D15- ...
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... D11 A15 A14 A13 A12 A11 D15-0 A15-0 4.11 Interrupts The SL11R provides 127 interrupt vectors. The first 64 vectors are hardware interrupts and the next 64 are software interrupts (see the [Ref. 1] SL11R_BIOS for more information). Document #: 38-08006 Rev USB GPIO PUD1 ...
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... The addresses from 0x0000 to 0x003E are read/write accessible and can be used for variables. 4.11.2 Interrupt Enable Register (0xC00E: R/W) This is a global hardware interrupt enable register that allows control of the hardware interrupt vectors. The SL11R BIOS default set-up of this register is 0x28 (i.e. USB and UART bits are set). D15 ...
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... The interrupts can be enabled for “Suspend mode” by the power down Register or enabled for interrupts by the Interrupt Enable Register. 4.11.4 Software Interrupts The SL11R allocates addresses from 0x0040 to 0x00FE for software interrupts. The software interrupt vectors are shown in Table 4-4: Document #: 38-08006 Rev. ** Timer1 Interrupt Enable ...
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... Notes: 6. These software vectors are reserved for the internal SL11R-BIOS. The user should not overwrite these functions. 7. These vectors are used as the data pointers. The user should not execute code (i.e. JMP or INT) to these vectors. See [Ref. 1] SL11R_BIOS for more information. ...
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... The SL11R BIOS uses GPIO28 for data transmit (TX) and GPIO27 for data receive (RX). These two pins cannot be used for any other purpose. Note: On reset, the SL11R BIOS will configure the UART to operate at 14,400 baud. Other parameters are: 1 stop bit, 8 data bits, no parity. ...
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... PROM/EPROM. The SL11R BIOS uses two GPIO pins, GPIO31 and GPIO30 to interface to an external serial EEPROM (see Figure 4-4): • GPIO31 is connected to the Serial Clock Input (SCL). ...
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... Pin 1 (A0), Pin 2 (A1), Pin 3 (A2), Pin 4 (GND) and Pin 7 Write Protect) are connected to Ground. Figure 4-4. 2-Wire Serial Interface 2K-byte Connection The current SL11R BIOS only support 2Kbyte serial EEPROM. To read and write to a device that is larger than 2Kbytes, the SL11R-BIOS requires additional serial EEPROM to be connected as shown in Figure 4-5. ...
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... Extended Memory Width ('0' = 16, ' Extended Memory Wait states ( External ROM Width ('0' = 16, ' External ROM wait states ( External RAM Width ('0' = 16, ' External RAM Wait States ( D11 D10 A21 A20 A19 RO1 RO0 RA3 RA2 A18 A17 A16 A15 A14 SL11R RA1 RA0 D0 A13 Page ...
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... The program code or data can be stored in either external RAM or external ROM. The SL11R allows extended data (video stored on an external EDO DRAM. The entire (video image) data can be transferred via DMA directly to DRAM without software intervention. The total DMA size can be up-to 2M-bytes. The SL11R processor can access DRAM data via the address space from 0x8000 to 0xBFFF ...
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... ROM will be (0xE800-0xC100), which is 9.75K-byte. The signal nXROMSEL on the SL11R (pin57) will be active when the CPU accesses the address from 0xC100 to 0xE7FF. The signal nXMEMSEL on the SL11R (pin58) will be active when the CPU accesses the address from 0x8000 to 0xBFFF. When bit 12 (ROM Merge Bit) of the Extended Memory Controller Register at address 0xC03A is ‘ ...
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... Timer 0 Count Register (0xC010: R/W) The SL11R BIOS uses the timer 0 for time-out function and power down mode. At the end of the power up, the SL11R BIOS disables the timer 0 interrupt. If you wish to use timer 0 for power down function, see the [Ref. 1] SL11R_BIOS for more information ...
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... The GPIO20 can be used for device low power mode; it will remove power from the peripherals in suspend mode. Once USB power is restored, the power to the peripherals may be enabled. The SL11R BIOS will execute the pull up interrupt upon power-up. To use this feature, the GPIO29 pin must be connected to the DATA+ line of the USB connector (see Figure below) ...
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... The default is continuous repeat. Individual Polarity bits for channels ’1’ is active high or rising edge pulse. Individual Enable bits for channels ’1’ enables. D11 D10 always '0' 's. Maximum Count Value. D11 D10 always '0' 's. Start Count for PWM Channel SL11R Page ...
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... Stop Count for PWM Channel 1. D11 D10 always ’0’ ’s. Start Count for PWM Channel 2. D11 D10 always ’0’ ’s. Stop Count for PWM Channel 2. D11 D10 always ’0’ ’s. Start Count for PWM Channel SL11R Page ...
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... SD7-SD0. In the 8/16-Bit DMA mode, the DMA data path can be configured as either 8 or 16. 4.18.1 DMA Control Register (0xC02A: R/W) External device data presented to S15-SD0/SD7-SD0 is automatically written into the RAM of the SL11R, under fast DMA control. The DMA must be enabled in the DMA Control and Address register. D2 ...
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... General Purpose IO mode (GPIO) In GPIO mode, the SL11R has general-purpose I/O signals available. However, there are 4 pins used by the UART and the 2-wire serial interface that cannot be used as the GPIO pins. A typical application for this GPIO is Parallel Port to USB. The SL11R executes at 48MHz -- fast enough to generate any Parallel Port timing ...
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... E24 E23 E22 Enable individual outputs, GPIO 31-16. Logic ’1’ enables. D11 D10 O11 O10 Output Pin Data D11 D10 O27 O26 Output Pin Data D11 D10 I11 I10 Input Pin data E21 E20 E19 E18 E17 E16 Page SL11R D0 ...
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... This mode includes the Mailbox Protocol and DMA Protocol. The Mailbox Protocol allows asynchronous exchange of data between an external Processor (i.e. DSP or Microprocessors) and the SL11R, via the bidirectional data port SD15-SD0 (GPIO15-0). The DMA Protocol allows the large data blocks to be transferred to or from SL11R memory devices via the 8/16-bit DMA port. ...
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... OUTBUFF Data Register (0xC0C4: R/W) The SL11R will write to this register and the external processor will read from this register with the ADDR signal set to one. The SL11R will receive an interrupt after the external processor finished reading (if the MBX interrupt is enabled in the Register 0xC00E) ...
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... SL11R DMA cycles to or from the external device (scanner, printer, camera, modem or etc.). The DREQ is asserted by the SL11R when data is ready to be sent or received. When the external device is ready to send Data, it asserts the nWRITE signal. Data must be available at this point. If the external device is ready to accept data, it asserts the nREAD signal. ...
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... Device and register address value from the SD7-SD0 Data Bus Read Data SD5 SD4 SD3 EPP data from the SD7-SD0 data bus Value output on GPIO21. from the GPIO8 line from GPIO9 SD2 SD1 SD0 SD2 SD1 SD0 INTR WAIT Page SL11R ...
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... D7-D0 P8-P1 Note: A write to this register causes the SL11R to write this out the corresponding GPIO pins (Except P6). The output value of the P6 will be the complement of the value written. 5.3.7 Serial Interface Registers The SL11R supports subset of an industry standard SPI serial interface, which provides the interface to serial interface device like Multi-Media or Memory Stick interface. 5.3.7.1 Serial Interface Control & ...
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... USB Host to the SL11R. Raw video data from the Camera is input to the SL11R on the 8-bit video data bus (SD7-SD0) using a combination of clock and control signals and 8 bit DMA. The signals include a clock (MCK0), Field Index (FI), Sync and blanking signals (SYNC, PBLK), and Drive signals (VD and HD) ...
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... EEPROM. (During this time the DSP drives the Serial Clock to the EEPROM and the CCS select line to the SL11R, EEP1 is driven high from the SL11R). After a timed interval, the AEEP line is driven low and the SL11R can now communicate to the camera via the Camera Serial Port ...
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... Input Data Register 1 I/O Control Register 1 DMA Control Register Low DMA Start Address Register High DMA Start Address Register Document #: 38-08006 Rev. ** D11 D10 R11 R10 Read Data from the SD7-SD0 Data Bus. SL11R Address Mode 0x0120 R/W 0x0122 R/W 0x0124 ...
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... UART Control Register UART Status Register UART Transmit Data Register UART Receive Data Register PWM Control Register PWM Maximum Count Register PWM Channel 0 Start Register PWM Channel 0 Stop Register Document #: 38-08006 Rev. ** SL11R Address Mode 0xC030 R/W 0xC032 R/W 0xC038 R/W ...
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... Bidir External Memory Data Bus, Data14 Bidir External Memory Data Bus, Data15 Output External Memory Address Bus, A20 Output External Memory Address Bus, A19 Output External Memory Address Bus, A18 SL11R Address Mode 0xC0EE R/W 0xC0F0 R/W 0xC0F2 R/W 0xC0F4 R/W ...
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... Active LOW, write to lower bank of External SRAM Output Active LOW, Write to upper bank of External SRAM Output Active LOW, Read from External SRAM or ROM Input Master Reset. SL11R Device active LOW reset input. Output Active low, DRAM Row Address Select Power +3.3 VDC Supply Power +3 ...
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... Same as above or GPIO22 Bidir Same as above or GPIO21 Bidir DMA Request Enable. DREQ indicates that SL11R is ready to accept or send data from/to an external device. DREQ along with nCS, nWRITE and nREAD bits are the DMA handshake signals for the main SDATA port, or GPIO20. Bidir ...
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... Output External Memory Address Bus, A13 Output External Memory Address Bus, A12 Output External Memory Address Bus, A11 Output External Memory Address Bus, A10 Output External Memory Address Bus, A9 Output External Memory Address Bus, A8 Output External Memory Address Bus, A7 SL11R Page ...
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... Active LOW, write to lower bank of External SRAM Output Active LOW, Write to upper bank of External SRAM Output Active LOW, Read from External SRAM or ROM Input Master Reset. SL11R Device active low reset input. Output Active low, DRAM Row Address Select Power +3.3 VDC Supply Power +3 ...
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... External Memory Data Bus, Data2 Bidir External Memory Data Bus, Data3 Bidir External Memory Data Bus, Data4 Bidir External Memory Data Bus, Data5 Bidir External Memory Data Bus, Data6 Bidir External Memory Data Bus, Data7 Bidir External Memory Data Bus, Data8 SL11R Page ...
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... Active LOW, write to lower bank of External SRAM Output Active LOW, Write to upper bank of External SRAM Output Active LOW, Read from External SRAM or ROM Input Master Reset. SL11R Device active low reset input. Output Active LOW, DRAM Row Address Select Power +3.3 VDC Supply Power +3 ...
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... UART Transmit Data (out), or GPIO28 GND Digital ground. GND Digital ground. Input UART Receive Data (in), or GPIO27 Bidir GPIO26 Bidir GPIO25, or IRQ1 (in) interrupts the SL11R processor Bidir IRQ0 (in) interrupts the SL11R processor or GPIO24 Bidir GPIO23 Bidir GPIO22 Output VIDEO Reset Pin Output ...
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... This document describes the SL11R CPU Instruction Set, Registers and Addressing modes, Instruction format, etc. The SL11R PROCESSOR uses a unified program and data memory space; although this RAM is also integrated into the SL11R core, provision has been made for external memory as well. ...
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... Instruction Format To understand addressing modes supported by the SL11R Processor, you must know how the instruction format is defined. In general, the instructions include four bits for the instruction opcode, six bits for the source operand, and six bits for the destination operand. ...
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... This section describes in detail the six-operand field bits referred to in the previous section as source and destination. Bear in mind that although the discussion refers to bits 0 through 5, the same bit definitions apply to the “source” operand field, bits 6 through 11. These are the basic addressing modes in the SL11R Processor. Mode ...
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... Byte-wide reads or writes are prohibited in indirect mode. • If R15 is addressed in Indirect with Index mode, it does not auto-increment or auto-decrement. SL11R - CPU Instruction Set The instruction set can be roughly divided into three classes of instructions: • Dual Operand Instructions (Instructions with two operands, a source and a destination) • ...
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... Flags Affected TEST bit 0111 [not saved]:= destination & source Flags Affected bit 1000 destination:= destination | source Flags Affected Document #: 38-08006 Rev source source source source source source source Destination Destination Destination Destination Destination Destination Destination Page SL11R ...
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... Note: Interrupt vectors 0 through 31 may be reserved for hardware interrupts, depending on the application. The condition (cccc) bits for all of the above instructions are defined as: Document #: 38-08006 Rev source cccc cccc cccc cccc 0000 0 int vector Destination Offset Destination 010111 Destination Page SL11R ...
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... Note: • For the SHR, SHL, ROR, ROL, ADDI and SUBI instructions, the three-bit count or n operand is incremented by 1 before it is used. • The SL11R QT assembler takes this into account. SHR bit: ...
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... Flags Affected NOT bit 1101111 destination:= ~destination Flags Affected NEG bit 1101111 destination:= -destination Flags Affected Document #: 38-08006 Rev count count count n n 000 (bitwise 1’s complement negation 001 (2’s complement negation destination destination destination destination destination destination destination SL11R Page ...
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... Flags Affected: C 7.21 Built-in Macros For the programmer’s convenience, the SL11R QT assembler implements several built-in macros. The table below shows the macros, and the mnemonics for the code that the assembler will generate for these macros. Macro Assembler will Generate ...
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... SL11R Processor Instruction Set Summary Mnemonic Operands MOV s,d Move ADD s,d Add ADDC s,d Add with carry SUB s,d Subtract s from d SUBB s,d Subtract s from d with carry CMP s,d Compare d with s AND s,d AND d with s TEST s,d Bit test d with s ...
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... SL11R - Electrical Specification 8.1 Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL11R. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Parameter Storage temperature ...
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... Series Resistance Shunt Capacitance Load Capacitance Driver Level rd Mode of Vibration 3 overtone 8.4 External Clock Input Characteristics (XTAL1) Parameter Clock Input Voltage @ XTAL1 (XTAL2 is Opened) Clock Frequency 8.5 SL11R DC Characteristics Parameter Description V Input Voltage LOW IL V Input Voltage HIGH IH V Output Voltage LOW OL (I ...
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... SL11R USB Transceiver Characteristics Parameter Description V Hysteresis On Input (Data+, Data–) IHYS V USB Input Voltage HIGH USBIH V USB Input Voltage LOW USBIL V USB Output Voltage HIGH USBOH V USB Output Voltage LOW USBOL [14] Z Output Impedance HIGH STATE USBH [14] Z Output Impedance LOW STATE ...
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... APW t nCS pulse width CPW t Read pulse width RPW t Read access time ACC t Read high to data hold RDH Note: RCLK is the resulting Clock (see Register 0xC006) Document #: 38-08006 Rev APW t CPW t RPW t RDH t ACC Data Valid Min. Typical SL11R Max Page ...
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... WCH t Write pulse width WRPW t Data setup to write high set-up DWS t Write high to data hold WDH Note: RCLK is the resulting Clock (see Register 0xC006) Document #: 38-08006 Rev APW t t CWS WCH t WRPW t WDH t DWS Data Valid Min. Typical SL11R Max. Page ...
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... DREQ nCS nWRITE D15-0 Parameter Description DCS DREQ high to CS low DWDH Write high to DREQ low hold DW DREQ high to write low 8.13 SL11R Signals Name convention Doc. Signal Name SL11R Pin Name /RAS nRAS /UCAS nCASH Dout Data15-0 Din Data15-0 /CS nXRAMSEL /WE (SRAM) nWRL & ...
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... Cycle time read RC t Data out to High Z OFF Note: This timing is base on EDO DRAM timing 16Mx16 devices. When the SL11R processor is set up for a higher speed (i.e. 48MHz clock), then the faster parts (i.e. 50ns or 60ns) should be used. Document #: 38-08006 Rev. ** Min. Typical Max ...
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... SL11R DRAM Read Cycle RAS UCAS LCAS t ASR Row Address WE Dout OE Document #: 38-08006 Rev RAS t RCD t CAS t RAD t RAH t t ASC CAH Column t CAC t RAC t OAC t OEP SL11R t RP Dout Page ...
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... SL11R DRAM Write Cycle RAS UCAS LCAS t ASR Row Address WE Din Document #: 38-08006 Rev RAS t RSH t t RCD CAS t CSH t RAH t t ASC CAH Column t WCS t WCH SL11R CRP Page ...
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... SL11R CAS-Before-RAS Refresh Cycle t RP nRAS RPC t t CSR CPN nCASL nCASH A11-0 t OFF Data15-0 Document #: 38-08006 Rev RAS RP RAS t RPC CHR CSR CPN High-Z SL11R CRP CHR Page ...
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... SL11R DRAM Page Mode Read Cycle RAS UCAS LCAS t t ASR RAH WE D out Document #: 38-08006 Rev RAS RCD CAS t CSH t t RAD t t Column t RCHA t CAL t t RCHR RAC t t OAC DZC High-Z t DZO t OEP SL11R CRP RDD t t OHR ...
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... DRAM Page Mode Write Cycle RAS UCAS LCAS t RAH Address Row out Document #: 38-08006 Rev RAS t RSH t t RCD CAS t CSH RAH CAH ASC Column t t WCS WCH t t RAH RAH High-Z SL11R Page ...
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... SL11R SRAM Read Cycle Address CS RD Din Parameter Description t CS low to RD low high to data hold RDH t CS high to data hold CDH [15 low time RPW t RD low to address valid AR [16] t RAM access to data valid AC Notes: 15. 0 wait state cycle. 16. t means at 0 wait states, with PCLK = 2/3 RCLK, the SRAM access time should be 12ns max. For a 1 wait state cycle, with PCLK = 2/3 RCLK, the SRAM AC access time should 31ns = 43ns max ...
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... SL11R SRAM Write Cycle Address CS WE Dout Parameter Description t Write address valid to WE low low to WE low CSW t Data valid to WE high DW [17 pulse width WPW t Data hold from WE high high to CS high WC Note: 17. This wait state with PCLK = 2/3 RCLK. For 2-wait states, add 31 ns. ...
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... T 1.0 s max 200 ns max. su1 hold1 T 4.5 s min. su2 T 100 ns max. hold2 Document #: 38-08006 Rev low T high T hold1 T hold2 EEDATA EECLK STOP See ATMEL Data Sheet for Complete Timing Detail SL11R Data Validity Data Change Data Stable Notes Page ...
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... WDA nWRITE low to nDTSRB or nASTRB low DAW nDTSRB or nASTRB high to nWRITE high WDH nDTSRB or nASTRB high to data hold Document #: 38-08006 Rev. ** RPW RDS RDH Data Valid Min WPW DAW WDA RPW WDH Data Valid Min. Typical Max Typical Max Page SL11R ...
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... Package information 9.1 Drawings and Dimensions Document #: 38-08006 Rev. ** SL11R Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. SL11R-IDE YYWWSQFP-1.2 XXXX Min. Typ. Max. 125°C 65°C/W 75°C/W ) 0.8W SL11R Page ...
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... Revision History Document Title: SL11R USB Controller/16-Bit RISC Processor Data Sheet Document Number: 38-08006 ISSUE REV. ECN NO. DATE ** 110565 12/14/01 Document #: 38-08006 Rev. ** ORIG. OF CHANGE DESCRIPTION OF CHANGE BHA Converted to Cypress Format from ScanLogic SL11R Page ...