SL11R Cypress Semiconductor Corp, SL11R Datasheet - Page 57

• Manufacturer Part Number: SL11R
• Description: IC MCU FULL SPD USB 16B 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL11R

• Applications: USB Microcontroller
• Core Processor: RISC
• Program Memory Type: Mask ROM (6 kB)
• Controller Series: USB Controller
• Ram Size: 3Kx8
• Interface: 2-Wire Serial, UART, USB
• Number Of I /o: 32
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1462

DVC 8-Bit DMA Mode Pin Assignment and Description (continued)
7.0
This is the preliminary specification for the SL11R Processor Instruction set.
7.1
This document describes the SL11R CPU Instruction Set, Registers and Addressing modes, Instruction format, etc. The SL11R
PROCESSOR uses a unified program and data memory space; although this RAM is also integrated into the SL11R core,
provision has been made for external memory as well.
The SL11R PROCESSOR engine incorporates 38 registers: fifteen general-purpose registers, a stack pointer, sixteen registers
mapped into RAM, a program counter, and a REGBANK register whose function will be described in a subsequent section.
The SL11R PROCESSOR engine supports byte and word addressing. Subsequent sections of this document will describe:
7.2
7.3
The SL11R Processor incorporates 16-bit general-purpose registers called R0..R15, a REGBANK register, and a program
counter, along with various other registers. The function of each register is defined as follows:
7.4
The general-purpose registers can be used to store intermediate results, and to pass parameters to and return them from
subroutine calls.
Document #: 38-08006 Rev. **
R0-R14
R15
PC
REGBANK
FLAGS
INTERRUPT ENABLE
• The SL11R PROCESSOR Engine (QT Engine) Register Set
• SL11R PROCESSOR Engine Instruction Format
• SL11R PROCESSOR Engine Addressing Modes
• SL11R PROCESSOR Engine Instruction Set
Pin Name
VDD
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
DI
Instruction Set Overview
Reset Vector
On receiving hardware reset, the SL11R Processor jumps to address 0xFFF0, which is an internal ROM
address.
Register Set
General-Purpose Registers
SL11R CPU Programming Guide
Name
Pin No.
100
91
92
93
94
95
96
97
98
99
GPIO pins
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
General Purpose Registers
Stack Pointer
Program Counter
Forms base address for registers R0-R15
Contains flags: defined below
Bit masks to enable/disable various interrupts
Pin Type
Power
Input
Input
Input
Input
Input
Input
Input
Input
Bidir
Serial EPROM Data Input
SDATA port bit 7, or GPIO7
SDATA port bit 6, or GPIO6
+3.3 VDC Supply
SDATA port bit 5, or GPIO5
SDATA port bit 4, or GPIO4
SDATA port bit 3, or GPIO3
SDATA port bit 2, or GPIO2
SDATA port bit 1, or GPIO1
SDATA port bit 0, or GPIO0
GPIO & DVC 8-bit DMA modes Pin Chip Revision 1.1
Function
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SL11R