CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 17

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The driving state of each GPIO pin is determined by the value
written to the pin’s Data Register
Table 7 on page
as shown in the GPIO Configuration Register
(Table 8 on page
basis, so all pins in a given port are configured together. The
possible port configurations are detailed in
Table 9. GPIO Port Output Control Truth Table and Interrupt Polarity
Q1, Q2, and Q3 discussed below are the transistors referenced
in
■
■
■
Table 10. Port 0 Interrupt Enable
Table 11. Port 1 Interrupt Enable
Document Number: 38-08001 Rev. *D
Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit
Port 0 Interrupt
Enable
Bit #
Bit Name
Read/Write
Reset
Port 1 Interrupt
Enable
Bit #
Bit Name
Read/Write
Reset
Output LOW Mode: The pin’s Data Register is set to ‘0’
Output HIGH Mode: The pin’s Data Register is set to 1 and the
Port Configuration Bits[1:0] is set to ‘10’
Resistive Mode: The pin’s Data Register is set to 1 and the Port
Configuration Bits[1:0] is set to ‘11’
Figure 3 on page
Writing ‘0’ to the pin’s Data Register puts the pin in output
LOW mode, regardless of the contents of the Port
Configuration Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3
is ON. The GPIO pin is driven LOW through Q3.
In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is
pulled up through Q2. The GPIO pin is capable of sourcing of
current.
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with
an internal 14 kresistor. In resistive mode, the pin may serve
as an input. Reading the pin’s Data Register returns a logic
HIGH if the pin is not driven LOW by an external source.
1
1
0
0
P0.7 Intr Enable P0.6 Intr Enable P0.5 Intr Enable P0.4 Intr Enable P0.3 Intr Enable P0.2 Intr Enable P0.1 Intr Enable P0.0 Intr Enable
P1.7 Intr Enable P1.6 Intr Enable P1.5 Intr Enable P1.4 Intr Enable
16) and by its associated Port Configuration bits
16). These ports are configured on a per-port
15. The available GPIO drive strength are:
W
W
7
0
7
0
1
0
1
0
(Table 4 on page 15
W
W
6
0
6
0
Table
0
1
0
1
0
1
0
1
9. As shown in
W
W
5
0
5
0
through
Output HIGH
Output LOW
Output LOW
Output LOW
Output LOW
Resistive
W
W
4
0
4
0
Hi-Z
Hi-Z
this table below, when a GPIO port is configured with CMOS
outputs, interrupts from that port are disabled.
During reset, all of the bits in the GPIO Configuration Register
are written with ‘0’ to select Hi-Z mode for all GPIO ports as the
default configuration.
■
GPIO Interrupt Enable Ports
Each GPIO pin can be individually enabled or disabled as an
interrupt source. The Port 0–3 Interrupt Enable registers provide
this feature with an interrupt enable bit for each GPIO pin. When
HAPI mode (discussed in
(HAPI) on page
including ports not used by HAPI, so GPIO pins cannot be used
as interrupt sources.
During a reset, GPIO interrupts are disabled by clearing all of the
GPIO interrupt enable ports. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input
pin. All GPIO pins share a common interrupt, as discussed in
GPIO/HAPI Interrupt on page
Hi-Z Mode: The pin’s Data Register is set to1 and Port
Configuration Bits[1:0] is set either ‘00’ or ‘01’
Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven
internally. In this mode, the pin may serve as an input.
Reading the Port Data Register returns the actual logic value
on the port pins.
P1.3 Intr Enabl
W
W
3
0
3
0
24) is enabled the GPIO interrupts are blocked,
P1.2 Intr Enable P1.1 Intr Enable P1.0 Intr Enable
0
1
0
1
0
1
0
1
W
W
2
0
2
0
Hardware Assisted Parallel Interface
29.
Interrupt Polarity
W
W
1
0
1
0
– (Falling Edge)
– (Falling Edge)
+ (Rising Edge)
CY7C64013C
CY7C64113C
Disabled
Disabled
Disabled
Disabled
Disabled
ADDRESS 0x04
ADDRESS 0x05
Page 17 of 53
W
W
0
0
0
0
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