CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 30

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When HAPI is enabled, the HAPI logic takes over the interrupt
vector and blocks any interrupt from the GPIO bits, including
ports/bits not being used by HAPI. Operation of the HAPI
interrupt is independent of the GPIO specific bit interrupt
enables, and is enabled or disabled only by bit 5 of the Global
Interrupt Enable Register
enabled. The settings of the GPIO bit interrupt enables on
ports/bits not used by HAPI still effect the CMOS mode operation
of those ports/bits. The effect of modifying the interrupt bits while
the Port Config bits are set to “10” is shown in
events that generate HAPI interrupts are described in
Assisted Parallel Interface (HAPI) on page
I
The I
I
This generally involves reading the I
Register
interrupt, loading/reading the I
and finally writing the Status and Control Register to initiate the
subsequent transaction. The interrupt indicates that status bits
are stable and it is safe to read and write the I
to
registers.
When enabled, the I
interrupts on completion of the following conditions. The refer-
enced bits are in the I
Document Number: 38-08001 Rev. *D
1. In slave receive mode, after the slave receives a byte of data:
2. In slave receive mode, after a stop bit is detected: The
2
2
C-compatible bus to signal the need for firmware interaction.
C Interrupt
GPIO
Pin
I2C-compatible Controller on page 22
The Addr bit is set, if this is the first byte since a start or restart
signal was sent by the external master. Firmware must read
or write the data register as necessary, then set the ACK, Xmit
MODE, and Continue/Busy bits appropriately for the next
byte.
Received Stop bit is set, if the stop bit follows a slave receive
transaction where the ACK bit was cleared to 0, no stop bit
detection occurs.
IRA
2
1 = Enable
0 = Disable
C interrupt occurs after various events on the
(Table 24 on page
2
2
C Status and Control Register.
C-compatible state machines generate
Port Interrupt
Enable Register
(Table 28 on page
22) to determine the cause of the
2
C Data Register as appropriate,
Configuration
Register
M
U
X
Port
2
C Status and Control
for details on the I
24.
2
Figure 8. GPIO Interrupt Structure
26) when HAPI is
C registers. Refer
Table
1 = Enable
0 = Disable
Hardware
9. The
(1 input per
OR Gate
GPIO pin)
2
C
(Bit 5, Register 0x20)
GPIO Interrupt
The Continue/Busy bit is cleared by hardware prior to interrupt
conditions 1 to 4. Once the Data Register has been read or
written, firmware should configure the other control bits and set
the Continue/Busy bit for subsequent transactions. Following an
interrupt from master mode, firmware should perform only one
write to the Status and Control Register that sets the
Continue/Busy bit, without checking the value of the
Continue/Busy bit. The Busy bit may otherwise be active and I
register contents may be changed by the hardware during the
transaction, until the I
USB Overview
The USB hardware consists of the logic for a full-speed USB
Port. The full-speed serial interface engine (SIE) interfaces the
microcontroller to the USB bus. An external series resistor (R
must be placed in series with the D+ and D– lines, as close to
3. In slave transmit mode, after the slave transmits a byte of
4. In master transmit mode, after the master sends a byte of
5. In master receive mode, after the master receives a byte of
6. When the master loses arbitration: This condition clears the
Global
Enable
data: The ACK bit indicates if the master that requested the
byte acknowledged the byte. If more bytes are to be sent,
firmware writes the next byte into the Data Register and then
sets the Xmit MODE and Continue/Busy bits as required.
data. Firmware should load the Data Register if necessary,
and set the Xmit MODE, MSTR MODE, and Continue/Busy
bits appropriately. Clearing the MSTR MODE bit issues a stop
signal to the I
data: Firmware should read the data and set the ACK and
Continue/Busy bits appropriately for the next byte. Clearing
the MSTR MODE bit at the same time causes the master state
machine to issue a stop signal to the I
leave the I
MSTR MODE bit and sets the ARB Lost/Restart bit
immediately and then waits for a stop signal on the
I
2
C-compatible bus to generate the interrupt.
1
GPIO Interrupt
Flip Flop
D
CLR
2
C-compatible hardware in the idle state.
Q
2
C-compatible bus and return to the idle state.
2
C interrupt occurs.
Interrupt
Encoder
Priority
2
CY7C64013C
CY7C64113C
C-compatible bus and
Interrupt
IRQout
Vector
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C
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