CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 25

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Status and Control Register
Table 27. Processor Status and Control Register
Bit 0: Run
Bit 1: Reserved
Bit 2: Interrupt Enable Sense
Bit 3: Suspend
Bit 4: Power-On Reset
Document Number: 38-08001 Rev. *D
Processor
Status and
Control
Bit #
Bit Name
Read/Write
Reset
This bit is manipulated by the HALT instruction. When Halt
is executed, all the bits of the Processor Status and Control
Register are cleared to 0. Since the run bit is cleared, the
processor stops at the end of the current instruction. The
processor remains halted until an appropriate reset occurs
(power-on or Watchdog). This bit should normally be
written as a ‘1.’
Bit 1 is reserved and must be written as a zero.
This bit indicates whether interrupts are enabled or
disabled. Firmware has no direct control over this bit as
writing a zero or one to this bit position has no effect on
interrupts. A ‘0’ indicates that interrupts are masked off and
a ‘1’ indicates that the interrupts are enabled. This bit is
further gated with the bit settings of the Global Interrupt
Enable Register
Interrupt Enable Register
Instructions DI, EI, and RETI manipulate the state of this
bit.
Writing a ‘1’ to the Suspend bit halts the processor and
cause the microcontroller to enter the suspend mode that
significantly reduces power consumption. A pending,
enabled interrupt or USB bus activity causes the device to
come out of suspend. After coming out of suspend, the
device resumes firmware execution at the instruction
following the IOWR which put the part into suspend. An
IOWR attempting to put the part into suspend is ignored if
USB bus activity is present. See
14
The Power-On Reset is set to ‘1’ during a power-on reset.
The firmware can check bits 4 and 6 in the reset handler
to determine whether a reset was caused by a power-on
condition or a Watchdog timeout. A POR event may be
followed by a Watchdog reset before firmware begins
executing, as explained below.
for more details on suspend mode operation.
Pending
IRQ
R
7
0
(Table 28 on page
Watchdog
Reset
R/W
6
0
(Table 29 on page
Suspend Mode on page
26) and USB End Point
USB Bus Reset
Interrupt
R/W
5
0
27).
Power-On
Reset
R/W
4
1
Bit 5: USB Bus Reset Interrupt
Bit 6: Watchdog Reset
Bit 7: IRQ Pending
The USB Bus Reset Interrupt bit is set when the USB Bus
Reset is detected on receiving a USB Bus Reset signal on
the upstream port. The USB Bus Reset signal is a
single-ended zero (SE0) that lasts from 12 to 16 µs. An
SE0 is defined as the condition in which both the D+ line
and the D– line are LOW at the same time.
The Watchdog Reset is set during a reset initiated by the
Watchdog Timer. This indicates the Watchdog Timer went
for more than t
clears. This can occur with a POR event, as noted below.
The IRQ pending, when set, indicates that one or more of
the interrupts has been recognized as active. An interrupt
remains pending until its interrupt enable bit is set
28 on page
globally enabled. At that point, the internal interrupt
handling sequence clears this bit until another interrupt is
detected as pending.
During power-up, the Processor Status and Control
Register is set to 00010001, which indicates a POR (bit 4
set) has occurred and no interrupts are pending (bit 7
clear). During the 96 ms suspend at start-up (explained in
Power-On Reset (POR) on page
also occurs unless this suspend is aborted by an upstream
SE0 before 8 ms. If a WDR occurs during the power-up
suspend interval, firmware reads 01010001 from the
Status and Control Register after power-up. Normally, the
POR bit should be cleared so a subsequent WDR can be
clearly identified. If an upstream bus reset is received
before firmware examines this register, the Bus Reset bit
may also be set.
During a Watchdog Reset, the Processor Status and
Control
01XX0001b, which indicates a Watchdog Reset (bit 6 set)
has occurred and no interrupts are pending (bit 7 clear).
The Watchdog Reset does not effect the state of the POR
and the Bus Reset Interrupt bits.
Suspend
R/W
3
0
Register(Table 27 on page
26,
Enable Sense
WATCH
Interrupt
Table 29 on page
R
2
0
(8 ms minimum) between Watchdog
Reserved
R/W
1
0
14), a Watchdog Reset
27) and interrupts are
CY7C64013C
CY7C64113C
ADDRESS 0xFF
25) is set to
Page 25 of 53
R/W
Run
0
1
(Table
[+] Feedback