CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 21

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit [7:0]: Timer lower 8 bits
Table 19. Timer MSB Register
Bit [3:0]: Timer higher nibble
I
Internal hardware supports communication with external devices
through two interfaces: a two-wire I
Table 20. HAPI/I
Note: I
described in
Bits [7,1:0] of the HAPI/I
out configuration of the HAPI and I
[5:2] are used in HAPI mode only, and are described in
Hardware Assisted Parallel Interface (HAPI) on page
Table 21 on page 22
Table 22 on page 22
Document Number: 38-08001 Rev. *D
Timer MSB
Bit #
Bit Name
Read/Write
Reset
2
I
Configuration
Bit #
Bit Name
Read/Write
Reset
2
C and HAPI Configuration Register
C
2
C-compatible function must be separately enabled as
I2C-compatible Controller on page
11
L3
I
2
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Reserved
2
C Position
C Configuration Register
R/W
7
0
7
0
-
10 9
L2
shows the HAPI port configurations, and
2
C Configuration Register control the pin
shows I
L1 L0
Reserved
Reserved
2
8
2
C pin location configuration
6
0
6
0
-
2
-
C-compatible interfaces. Bits
C-compatible interface, and
7
Reserved
LEMPTY
6
Polarity
Figure 5. Timer Block Diagram
R/W
22.
5
0
5
0
-
5
24.
4
Reserved
Polarity
DRDY
R/W
4
0
4
0
-
3
Bit [7:4]: Reserved
a HAPI for 1, 2, or 3 byte transfers. The I
and HAPI functions, discussed in detail in
Controller on page 22
(HAPI) on page
Table
options. These I
in certain packages, and to allow simultaneous HAPI and
I
HAPI operation is enabled whenever either HAPI Port Width Bit
(Bit 1 or 0) is non-zero. This affects GPIO operation as described
in
I
in
2
2
C-compatible operation.
C-compatible blocks must be separately enabled as described
I2C-compatible Controller on page
Hardware Assisted Parallel Interface (HAPI) on page
2
Timer Bit 11
21). All bits of this register are cleared on reset.
Empty
Latch
R
R
3
0
3
0
1
8
2
0
24, share a common configuration register (see
C-compatible options exist due to pin limitations
Timer Bit 10
Ready
Data
and
R
R
2
0
2
0
Hardware Assisted Parallel Interface
1.024-ms Interrupt
128-
1-MHz Clock
To Timer Register
HAPI Port Width
µ
Timer Bit 9
s Interrupt
Bit 1
R/W
R
1
0
1
0
22.
2
C-compatible interface
CY7C64013C
CY7C64113C
ADDRESS 0x25
ADDRESS 0x09
HAPI Port Width
Timer Bit 8
I2C-compatible
Page 21 of 53
Bit 0
R/W
R
0
0
0
0
24.
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