CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 32

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 3 : Bus Activity
Bits 4 and 5 : D– Upstream and D+ Upstream
Bit 6 : Endpoint Mode
Bit 7 : Endpoint Size
Table 33. USB Device Address Registers
Bits[6..0] :Device Address
Bit 7
Table 34. Memory Allocation for Endpoints
When the SIE writes data to a FIFO, the internal data bus is
driven by the SIE; not the CPU. This causes a short delay in the
CPU operation. The delay is three clock cycles per byte. For
example, an 8-byte data write by the SIE to the FIFO generates
a delay of 2 µs (3 cycles/byte * 83.33 ns/cycle * 8 bytes).
Document Number: 38-08001 Rev. *D
USB Device
Address
Bit #
Bit Name
Read/Write
Reset
unused
unused
Label
EPA2
EPA1
EPA0
This is a “sticky” bit that indicates if any non-idle USB event
has occurred on the upstream USB port. Firmware should
check and clear this bit periodically to detect any loss of
bus activity. Writing a ‘0’ to the Bus Activity bit clears it,
while writing a ‘1’ preserves the current value. In other
words, the firmware can clear the Bus Activity bit, but only
the SIE can set it.
These bits give the state of each upstream port pin individ-
ually: 1 = HIGH, 0 = LOW.
This bit used to configure the number of USB endpoints.
See
description.
Firmware writes this bits during the USB enumeration pro-
cess to the non-zero address assigned by the USB host.
Must be set by firmware before the SIE can respond to
USB traffic to the Device Address.
Bit 7 (Device Address Enable) in the USB Device Address
Register must be set by firmware before the SIE can
respond to USB traffic to this address. The Device
Addresses in bits [6:0] are set by firmware during the USB
:Device Address Enable
USB Device Endpoints on page 32
Address
0xD8
Start
0xE0
0xE8
0xF0
0xF8
[0,0]
Device Address
Enable
R/W
7
0
Size
8
8
8
8
8
Device Address
Bit 6
unused
unused
R/W
Label
EPA0
EPA1
EPA2
6
0
USB Status And Control Register (0x1F) Bits [7, 6]
Device Address
Address
0xC0
Start
0xA8
0xB0
0xB8
0xE0
[1,0]
Bit 5
R/W
5
0
for a detailed
Size
Device Address
32
32
8
8
8
Bit 4
R/W
4
0
Label
EPA4
EPA3
EPA2
EPA1
EPA0
USB Serial Interface Engine Operation
USB Device Address A includes up to five endpoints: EPA0,
EPA1, EPA2, EPA3, and EPA4. Endpoint (EPA0) allows the USB
host to recognize, set-up, and control the device. In particular,
EPA0 is used to receive and transmit control (including set-up)
packets.
USB Device Address
The USB Controller provides one USB Device Address with five
endpoints. The USB Device Address Register contents are
cleared during a reset, setting the USB device address to zero
and marking this address as disabled.
of the USB Address Registers.
USB Device Endpoints
The CY7C64x13C controller supports one USB device address
and five endpoints for communication with the host. The
configuration of these endpoints, and associated FIFOs, is
controlled by bits [7,6] of the USB Status and Control Register
(0x1F). Bit 7 controls the size of the endpoints and bit 6 controls
the number of endpoints. These configuration options are
detailed in
table can be used by the firmware as additional user RAM space.
USB Control Endpoint Mode Register
All USB devices are required to have a Control Endpoint 0
(EPA0) that is used to initialize and control each USB address.
Endpoint 0 provides access to the device configuration
information and allows generic USB status and control accesses.
Device Address
This bit used to configure the number of USB endpoints.
See
description.
enumeration process to the non-zero address assigned by
the USB host.
Address
Bit 3
R/W
3
0
0xD8
Start
0xE0
0xE8
0xF0
0xF8
[0,1]
USB Device Endpoints on page 32
Table
34. The “unused” FIFO areas in the following
Device Address
Size
Bit 2
R/W
8
8
8
8
8
2
0
Label
EPA1
EPA2
EPA4
EPA3
EPA0
Device Address
Bit 1
R/W
1
0
Table 33
Address
0xC0
Start
0xB0
0xA8
0xB8
0xE0
[1,1]
ADDRESSES
CY7C64013C
CY7C64113C
Device Address
shows the format
Page 32 of 53
for a detailed
Bit 0
R/W
0
0
Size
32
32
8
8
8
0x10
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