MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 124

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Floating-Point Unit
6.1.3.4 ACCRUED EXCEPTION BYTE. The AEXC byte contains five exception bits (see
Figure 6-7) that the IEEE 754 standard requires for exception-disabled operations. These
exceptions are logical combinations of the bits in the EXC byte. The AEXC byte contains the
history of all floating-point exceptions that have occurred since the user last cleared the
AEXC byte. In normal operations, only the user clears this byte by writing to the FPSR; how-
ever, a reset or a restore operation of the null state can also clear the AEXC byte.
Many users elect to disable traps for all or part of the floating-point exception classes. The
AEXC byte makes it unnecessary to poll the EXC byte after each floating-point instruction.
At the end of most operations (FMOVEM and FMOVE excluded), the bits in the EXC byte
are logically combined to form an AEXC value that is logically ORed into the existing AEXC
byte. This operation creates sticky floating-point exception bits in the AEXC byte that the
user needs to poll only once (i.e., at the end of a series of floating-point operations). A sticky
bit is one that remains set until the user clears it.
Setting or clearing the AEXC bits neither causes nor prevents an exception. The following
equations show the comparative relationship between the EXC byte and AEXC byte. Com-
paring the current value in the AEXC bit with a combination of bits in the EXC byte derives
a new value in the corresponding AEXC bit. These equations apply to setting the AEXC bits
at the end of each operation affecting the AEXC byte:
6-6
SIGNALING NOT-A-NUMBER
OPERAND ERROR
BRANCH/SET ON
UNORDERED
OVERFLOW
IOP
Figure 6-7. Floating-Point Accrued Exception Byte (FPSR)
7
Figure 6-6. Floating-Point Exception Status Byte (FPSR)
OVFL
BSUN
6
15
UNFL
SNAN
5
14
M68060 USER’S MANUAL
DZ
OPERR
4
13
INEX
3
OVFL
12
2
UNFL
11
RESERVED
DZ
10
INEX2
0
9
DIVIDE-BY-ZERO
UNDERFLOW
OVERFLOW
INVALID OPERATION
INEXACT
INEX1
8
INEXACT DECIMAL
INPUT
INEXACT OPERATION
DIVIDE-BY-ZERO
UNDERFLOW
MOTOROLA