MC68EC000EI16 Freescale Semiconductor, MC68EC000EI16 Datasheet
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MOTOROLA M68000 FAMILY Programmer’s Reference Manual (Includes CPU32 Instructions) MOTOROLA INC., 1992 ...
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Paragraph Number 1.1 Integer Unit User Programming Model 1-2 1.1.1 Data Registers (D7 – D0) ...
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TABLE OF CONTENTS ( Continued ) Paragraph Number 1.7.2 Organization of Integer Data Formats in Memory . . . . . . . . . . . . . . . 1-27 1.7.3 Organization of Fpu Data Formats in Registers ...
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TABLE OF CONTENTS ( Continued ) Paragraph Number 3.1.3 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TABLE OF CONTENTS ( Continued ) Paragraph Number 8.1.1 Coprocessor ID Field ...
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TABLE OF CONTENTS ( Concluded ) Paragraph Number C.1 S-Record Content ...
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Figure Number 1-1 M68000 Family User Programming Model....................................................... 1-2 1-2 M68000 Family Floating-Point Unit User Programming Model ........................ 1-4 1-3 Floating-Point Control Register ........................................................................ 1-5 1-4 FPSR Condition Code Byte.............................................................................. 1-6 1-5 FPSR Quotient Code Byte ............................................................................... 1-6 1-6 FPSR ...
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LIST OF FIGURES (Concluded) Figure Number B-5 Six-Word Stack Frame, Format $2...................................................................B-4 B-6 MC68040 Floating-Point Post-Instruction Stack Frame, Format $3.................B-4 B-7 MC68EC040 and MC68LC040 Floating-Point Unimplemented Stack Frame, Format $4 ..................................................................................B-5 B-8 MC68040 Access Error Stack Frame, Format $7 ...........................................B-5 ...
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Table Number 1-1 Supervisor Registers Not Related To Paged Memory Management .............. 1-9 1-2 Supervisor Registers Related To Paged Memory Management................... 1-10 1-3 Integer Data Formats .................................................................................... 1-15 1-4 Single-Precision Real Format Summary Data Format .................................. 1-21 1-5 Double-Precision Real ...
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LIST OF TABLES (Continued) Table Number 7-1 MC68020 Instructions Not Supported ............................................................. 7-1 7-2 M68000 Family Addressing Modes................................................................. 7-2 7-3 CPU32 Instruction Set..................................................................................... 7-3 8-1 Conditional Predicate Field Encoding ............................................................. 8-3 8-2 Operation Code Map....................................................................................... 8-4 A-1 M68000 Family Instruction ...
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SECTION 1 INTRODUCTION This manual contains detailed information about software instructions used by the microprocessors and coprocessors in the M68000 family, including: MC68000 — 16-/32-Bit Microprocessor MC68EC000 — 16-/32-Bit Embedded Controller MC68HC000 — Low Power 16-/32-Bit Microprocessor MC68008 — 16-Bit ...
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Introduction 1.1 INTEGER UNIT USER PROGRAMMING MODEL Figure 1-1 illustrates the integer portion of the user programming model. It consists of the following registers: • 16 General-Purpose 32-Bit Registers (D7 – D0, A7 – A0) • 32-Bit Program Counter (PC) ...
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Program Counter The PC contains the address of the instruction currently executing. During instruction execution and exception processing, the processor automatically increments the contents or places a new value in the PC. For some addressing modes, the PC can ...
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Introduction C—Carry Set if a carry out of the most significant bit of the operand occurs for an addition borrow occurs in a subtraction; otherwise clear. 1.2 FLOATING-POINT UNIT USER PROGRAMMING MODEL The following paragraphs describe the ...
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Floating-Point Control Register (FPCR) The FPCR (see Figure 1-3) contains an exception enable (ENABLE) byte and a mode control (MODE) byte. The user can read or write to the FPCR. Motorola reserves bits 31 – 16 for future definition; ...
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Introduction to effective address, move multiple floating-point data register, and move system control register instructions do not affect the FPCC Figure 1-4. FPSR Condition Code Byte 1.2.3.2 QUOTIENT BYTE. The quotient byte contains the seven least significant ...
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ACCRUED EXCEPTION BYTE. The AEXC byte contains five exception bits (see Figure 1-7) required by the IEEE 754 standard for trap disabled operations. These exceptions are logical combinations of the bits in the EXC byte. The AEXC byte contains ...
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Introduction 1.2.4 Floating-Point Instruction Address Register (FPIAR) The integer unit can be executing instructions while the FPU is simultaneously executing a floating-point instruction. Additionally, the FPU can concurrently execute two floating-point instructions. Because of this nonsequential instruction execution, the PC ...
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Not Related To Paged Memory Management 68000 68008 68HC000 68HC001 Registers 68EC000 68010 AC1, AC0 ACUSR CAAR CACR DACR1, DACR0 DFC x DTT1, DTT0 IACR1, IACR0 ITT1, ITT0 MSP SFC SSP/ISP x x TT1, TT0 VBR ...
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Introduction Related To Paged Memory Management Registers AC CAL CRP DRP PCSR PMMUSR, MMUSR SCC SRP TC URP VAL AC CAL CRP DRP PCSR PMMUSR = MMUSR SCC SRP TC URP VAL 1.3.1 Address Register 7 (A7) In the supervisor ...
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T0 is always zero, and only one system stack where the M-bit is always zero. I2, I1, and I0 define the interrupt mask level. SYSTEM BYTE TRACE ENABLE SUPERVISOR/USER STATE ...
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Introduction 1.3.6 Transparent Translation/access Control Registers Transparent translation is actually a misnomer since the whole address space transparently translates in an embedded control environment with no on-chip MMU present as well as in processors that have built-in MMUs. For processors ...
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E—Enable 0 = Transparent translation/access control disabled 1 = Transparent translation/access control enabled CI—Cache Inhibit 0 = Caching allowed 1 = Caching inhibited R/W—Read/Write 0 = Only write accesses permitted 1 = Only read accesses permitted R/WM—Read/Write Mask 0 = ...
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Introduction Address Mask This 8-bit field contains a mask for the address base field. Setting a bit in this field causes the corresponding bit in the address base field to be ignored. Blocks of memory larger than 16 Mbytes can ...
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Operand Data Format Bit Bit Field Binary-Coded Decimal (BCD) Byte Integer Word Integer Long-Word Integer Quad-Word Integer 16-Byte 1.5 FLOATING-POINT DATA FORMATS The following paragraphs describe the FPU’s operand data formats. The FPU supports seven data formats. There are three ...
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Introduction SIGN OF MANTISSA SIGN OF EXPONENT USED ONLY FOR ± INFINITY OR NANS EXP 0 DIGIT 15 DIGIT 14 DIGIT 7 DIGIT 6 32 NOTE: XXXX indicates “don't care", which is zero when written ...
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The IEEE 754 standard has created the term significand to bridge the difference between mantissa and fraction and to avoid the historical implications of the term mantissa. The IEEE 754 standard defines a significand as the component of a binary ...
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Introduction 1.6.1 Normalized Numbers Normalized numbers encompass all numbers with exponents laying between the maximum and minimum values. Normalized numbers can be positive or negative. For normalized numbers in single and double precision the implied integer bit is one. In ...
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Zeros Zeros can be positive or negative and represent the real values + 0.0 and – 0.0 (see Figure 1-15). EXPONENT = 0 SIGN OF MANTISSA 1.6.4 Infinities Infinities can be positive or negative and represent ...
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Introduction SNAN can be used as an escape mechanism for a user-defined, non-IEEE data type. The FPU never creates an SNAN resulting from an operation. The IEEE specification defines NAN processing used as an input to an operation. A nonsignaling ...
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Table 1-4. Single-Precision Real Format Summary Data Format Sign (s) Biased Exponent (e) Fraction (f) Total Positive Fraction Negative Fraction Bias of Biased Exponent Range of Biased Exponent Range of Fraction Fraction Relation to Representation of Real Numbers Biased Exponent ...
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Introduction Table 1-5. Double-Precision Real Format Summary Sign (s) Biased Exponent (e) Fraction (f) Total Positive Fraction Negative Fraction Bias of Biased Exponent Range of Biased Exponent Range of Fraction Fraction Relation to Representation of Real Numbers Biased Exponent Format ...
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Table 1-6. Extended-Precision Real Format Summary Sign (s) Biased Exponent (e) Zero, Reserved (u) Explicit Integer Bit (j) Mantissa (f) Total Input Output Positive Mantissa Negative Mantissa Bias of Biased Exponent Range of Biased Exponent Explicit Integer Bit Range of ...
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Introduction Table 1-6. Extended-Precision Real Sign Explicit Integer Bit Biased Exponent Format Maximum Mantissa Representation of Fraction Nonsignaling Signaling Nonzero Bit Pattern Created by User Fraction When Created by FPCP Approximate Ranges Maximum Positive Normalized Minimum Positive Normalized Minimum Positive ...
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ORGANIZATION OF DATA IN REGISTERS The following paragraphs describe data organization within the data, address, and control registers. 1.7.1 Organization of Integer Data Formats in Registers Each integer data register is 32 bits wide. Byte and word operands occupy ...
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Introduction 31 30 MSB 31 NOT USED 31 NOT USED 31 MSB 63 MSB 31 31 OFFSET WIDTH + OFFSET > 32, BIT FIELD WRAPS AROUND WITHIN THE REGISTER. Figure 1-18. Organization ...
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Control registers vary in size according to function. Some control registers have undefined bits reserved for future definition by Motorola. Those particular bits read as zeros and must be written as zeros for future compatibility. All operations to the SR ...
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Introduction Figure 1-21 illustrates the organization of IU data formats in memory. A base address that selects one byte in memory, the base byte, specifies a bit number that selects one bit, the bit operand, in the base byte. The ...
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BYTE n – 1 ADDRESS BYTE n – 1 ADDRESS BYTE n – BYTE n – Figure 1-21. Memory Organization for ...
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Introduction 1.7.3 Organization of Fpu Data Formats in Registers and Memory The eight, 80-bit floating-point data registers are analogous to the integer data registers and are completely general purpose (i.e., any instruction may use any register). The MC68040 supports only ...
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SECTION 2 ADDRESSING CAPABILITIES Most operations take asource operand and destination operand, compute them, and store the result in the destination location. Single-operand operations take a destination operand, compute it, and store the result in the destination location. External microprocessor ...
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Addressing Capabilities An instruction specifies the function to be performed with an operation code and defines the location of every operand. Instructions specify an operand location by register specification, the instruction’s register field holds the register’s number; by effective address, ...
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Table 2-1. Instruction Word Format Field Definitions Field Mode Register D/A W/L Scale SIZE I/IS For effective addresses that use a full extension word format, the index suppress (IS) bit and the index/indirect selection (I/IS) field determine ...
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Addressing Capabilities Table 2-2. IS-I/IS Memory Indirect Action Encodings IS Index/Indirect 0 000 0 001 0 010 0 011 0 100 0 101 0 110 0 111 1 000 1 001 1 010 1 011 1 100–111 2.2 EFFECTIVE ADDRESSING ...
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Data Register Direct Mode In the data register direct mode, the effective address field specifies the data register containing the operand. GENERATION: ASSEMBLER SYNTAX: EA MODE FIELD: EA REGISTER FIELD: NUMBER OF EXTENSION WORDS: DATA REGISTER 2.2.2 Address Register ...
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Addressing Capabilities 2.2.4 Address Register Indirect with Postincrement Mode In the address register indirect with postincrement mode, the operand is in memory. The effective address field specifies the address register containing the address of the operand in memory. After the ...
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Address Register Indirect with Predecrement Mode In the address register indirect with predecrement mode, the operand is in memory. The effective address field specifies the address register containing the address of the operand in memory. Before the operand address ...
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Addressing Capabilities 2.2.6 Address Register Indirect with Displacement Mode In the address register indirect with displacement mode, the operand is in memory. The sum of the address in the address register, which the effective address specifies, plus the sign- extended ...
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Address Register Indirect with Index (8-Bit Displacement) Mode This addressing mode requires one extension word that contains an index register indicator and an 8-bit displacement. The index register indicator includes size and scale information. In this mode, the operand ...
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Addressing Capabilities 2.2.8 Address Register Indirect with Index (Base Displacement) Mode This addressing mode requires an index register indicator and an optional 16- or 32-bit sign- extended base displacement. The index register indicator includes size and scaling information. The operand ...
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Memory Indirect Postindexed Mode In this mode, both the operand and its address are in memory. The processor calculates an intermediate indirect memory address using a base address register and base displacement. The processor accesses a long word at ...
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Addressing Capabilities 2.2.10 Memory Indirect Preindexed Mode In this mode, both the operand and its address are in memory. The processor calculates an intermediate indirect memory address using a base address register, a base displacement, and the index operand (Xn.SIZE*SCALE). ...
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Program Counter Indirect with Displacement Mode In this mode, the operand is in memory. The address of the operand is the sum of the address in the program counter (PC) and the sign-extended 16-bit displacement integer in the extension ...
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Addressing Capabilities 2.2.12 Program Counter Indirect with Index (8-Bit Displacement) Mode This mode is similar to the mode described in 2.2.7 Address Register Indirect with Index (8-Bit Displacement) Mode , except the PC is the base register. The operand is ...
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Program Counter Indirect with Index (Base Displacement) Mode This mode is similar to the mode described in 2.2.8 Address Register Indirect with Index (Base Displacement) Mode , except the PC is the base register. It requires an index register ...
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Addressing Capabilities 2.2.14 Program Counter Memory Indirect Postindexed Mode This mode is similar to the mode described in 2.2.9 Memory Indirect Postindexed Mode , but the PC is the base register. Both the operand and operand address are in memory. ...
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Program Counter Memory Indirect Preindexed Mode This mode is similar to the mode described in 2.2.10 Memory Indirect Preindexed Mode , but the PC is the base register. Both the operand and operand address are in memory. The processor ...
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Addressing Capabilities 2.2.16 Absolute Short Addressing Mode In this addressing mode, the operand is in memory, and the address of the operand is in the extension word. The 16-bit address is sign-extended to 32 bits before it is used. . ...
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Immediate Data In this addressing mode, the operand is in one or two extension words. Table 2-3 lists the location of the operand within the instruction word format. The immediate data format is as follows: GENERATION: ASSEMBLER SYNTAX: EA ...
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Addressing Capabilities Table 2-4. Effective Addressing Modes and Categories Addressing Modes Register Direct Data Address Register Indirect Address Address with Postincrement Address with Predecrement Address with Displacement Address Register Indirect with Index 8-Bit Displacement Base Displacement Memory Indirect Postindexed Preindexed ...
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BRIEF EXTENSION WORD FORMAT COMPATIBILITY Programs can be easily transported from one member of the M68000 family to another in an upward-compatible fashion. The user object code of each early member of the family, which is upward compatible with ...
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Addressing Capabilities 2.5 FULL EXTENSION ADDRESSING MODES The full extension word format provides additional addressing modes for the MC68020, MC68030, and MC68040. There are four elements common to these full extension addressing modes: a base register (BR), an index register ...
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SIMPLE ARRAY (SCALE = RECORD OF 4 BYTES (SCALE = NOTE: Regardless of array structure, software increments index by the appropriate amount to point to next ...
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Addressing Capabilities 2.5.1 No Memory Indirect Action Mode No memory indirect action mode uses BR, Xn with its modifiers, and bd to calculate the address of the required operand. Data register indirect (Dn) and absolute address with index (bd,Xn.SIZE*SCALE) are ...
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Memory Indirect Modes Memory indirect modes fetch two operands from memory. The BR and bd evaluate the address of the first operand, intermediate memory pointer (IMP). The value of IMP and the od evaluates the address of the second ...
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Addressing Capabilities Figure 2-6. Memory Indirect with Preindex 2.5.2.2 MEMORY INDIRECT WITH POSTINDEX. The Xn is allocated to evaluate the address of the second operand. Figure 2-7 illustrates the memory indirect with post-indexing mode ...
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Figure 2-7. Memory Indirect with Postindex 2.5.2.3 MEMORY INDIRECT WITH INDEX SUPPRESSED. The Xn is suppressed. Figure 2-8 illustrates the memory indirect with index suppressed mode ...
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Addressing Capabilities 2.6 OTHER DATA STRUCTURES Stacks and queues are common data structures. The M68000 family implements a system stack and instructions that support user stacks and queues. 2.6.1 System Stack Address register seven (A7) is the system stack pointer. ...
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To implement stack growth from low memory to high memory, use (An push data on the stack and -(An) to pull data from the stack. After either a push or pull operation, the address register points to the ...
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Addressing Capabilities After a put operation, the put address register points to the last item placed in the queue; the unchanged get address register points to the last item removed from the queue. After a get operation, the get address ...
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SECTION 3 INSTRUCTION SET SUMMARY This section briefly describes the M68000 family instruction set, using Motorola,s assembly language syntax and notation. It includes instruction set details such as notation and format, selected instruction examples, and an integer condition code discussion. ...
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Instruction Set Summary Table 3-1. Notational Conventions Single- And Double Operand Operations Arithmetic addition or postincrement indicator. + Arithmetic subtraction or predecrement indicator. – Arithmetic multiplication. Arithmetic division or conjunction symbol. Invert; operand is logically complemented. ~ Logical AND Logical ...
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Table 3-1. Notational Conventions (Continued) + inf Positive Infinity <fmt> Operand Data Format: Byte (B), Word (W), Long (L), Single (S), Double (D), Extended (X), or Packed (P Specifies a signed integer data type (twos complement) of ...
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Instruction Set Summary Table 3-1. Notational Conventions (Concluded) * General Case C Carry Bit in CCR cc Condition Codes from CCR FC Function Code N Negative Bit in CCR U Undefined, Reserved for Motorola Use. V Overflow Bit in CCR ...
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Data Movement Instructions The MOVE and FMOVE instructions with their associated addressing modes are the basic means of transferring and storing addresses and data. MOVE instructions transfer byte, word, and long-word operands from memory to memory, memory to register, ...
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Instruction Set Summary Table 3-2. Data Movement Operation Format Instruction Operand Syntax EXG Rn, Rn FMOVE FPm,FPn <ea>,FPn FPm,<ea> <ea>,FPcr FPcr,<ea> FSMOVE, FPm,FPn FDMOVE <ea>,FPn FMOVEM 1 <ea>,<list> <ea>,Dn 1 <list> ,<ea> Dn,<ea> LEA <ea>,An LINK An,#<d> MOVE <ea>,<ea> MOVE16 ...
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A set of extended instructions provides multiprecision and mixed-size arithmetic: ADDX, SUBX, EXT, and NEGX. Refer to Table 3-3 for a summary of the integer arithmetic operations. In Table 3-3, X refers to the X-bit in the CCR. Table 3-3. ...
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Instruction Set Summary 3.1.3 Logical Instructions The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provides these logical operations with ...
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Table 3-5. Shift and Rotate Operation Format Operand Syntax Instruction ASL Dn data , Dn ea ASR Dn data , Dn ea LSL Dn data , Dn ea LSR Dn data , ...
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Instruction Set Summary 3.1.5 Bit Manipulation Instructions BTST, BSET, BCLR, and BCHG are bit manipulation instructions. All bit manipulation operations can be performed on either registers or memory. The bit number is specified either as immediate data or in the ...
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Binary-Coded Decimal Instructions Five instructions support operations on binary-coded decimal (BCD) numbers. The arithmetic operations on packed BCD numbers are ABCD, SBCD, and NBCD. PACK and UNPK instructions aid in the conversion of byte-encoded numeric data, such as ASCII ...
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Instruction Set Summary Table 3-9. Program Control Operation Format Instruction Operand Syntax Bcc, FBcc <label> DBcc, FDBcc Dn,<label> Scc, FScc <ea> BRA <label> BSR <label> JMP <ea> JSR <ea> NOP none FNOP none RTD #<data> RTR none RTS none TST ...
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Table 3-10. System Control Operation Format Operand Instruction Syntax ANDI to SR #<data>,SR EORI to SR #<data>,SR FRESTORE <ea> FSAVE <ea> MOVE to SR <ea>,SR MOVE from SR SR,<ea> MOVE USP USP,An An,USP MOVEC Rc,Rn Rn,Rc MOVES Rn,<ea> <ea>,Rn ORI ...
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Instruction Set Summary 3.1.10 Cache Control Instructions (MC68040) The cache instructions provide maintenance functions for managing the instruction and data caches. CINV invalidates cache entries in both caches, and CPUSH pushes dirty data from the data cache to update memory. ...
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Memory Management Unit (MMU) Instructions The PFLUSH instructions flush the address translation caches (ATCs) and can optionally select only nonglobal entries for flushing. PTEST performs a search of the address translation tables, stores the results in the MMU status ...
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Instruction Set Summary Table 3-14. Dyadic Floating-Point Operation Format Operand Instruction Syntax F<dop> <ea>,FPn FPm,FPn NOTE: < dop > is any one of the dyadic operation specifiers. Table 3-15. Dyadic Floating-Point Operations Instruction FADD, FSADD, FDADD FCMP FDIV, FSDIV, FDDIV ...
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Table 3-17. Monadic Floating-Point Operations Instruction Operation FABS Absolute Value FACOS Arc Cosine FASIN Arc Sine FATAN Hyperbolic Art Tangent FCOS Cosine FCOSH Hyperbolic Cosine FETOX x e FETOXM1 x – FGETEXP Extract Exponent FGETMAN Extract Mantissa FINT ...
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Instruction Set Summary Table 3-18. Integer Unit Condition Code Computations Operations ABCD ADD, ADDI, ADDQ ADDX AND, ANDI, EOR, EORI, MOVEQ, MOVE, OR, ORI, CLR, EXT, EXTB, NOT, TAS, TST CHK CHK2, CMP2 SUB, SUBI, SUBQ SUBX CAS, CAS2, CMP, ...
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Table 3-18. Integer Unit Condition Code Computations (Continued) Operations LSR ( ROXL ( ROL ROL ( ASR, LSR, ROXR ASR, LSR ( ROXR ( ROR ROR ( ...
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Instruction Set Summary 3.3 INSTRUCTION EXAMPLES The following paragraphs provide examples of how to use selected instructions. 3.3.1 Using the Cas and Cas2 Instructions The CAS instruction compares the value in a memory location with the value in a data ...
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The extract bit field unsigned (BFEXTU) also loads a bit field, but zero fills the unused portion of the destination register. The set bit field (BFSET) instruction sets all the bits ...
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Instruction Set Summary functions, software supports remainder and integer part; the FPU also supports the nontranscendental operations of absolute value, negate, and test. Most floating-point instruction descriptions include an operation table. This table lists the resulting data types for the ...
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FLOATING-POINT COMPUTATIONAL ACCURACY Representing a real number in a binary format of finite precision is problematic. If the number cannot be represented exactly, a round-off error occurs. Furthermore, when two of these inexact numbers are used in a calculation, ...
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Instruction Set Summary 3.5.1 Intermediate Result All FPU calculations use an intermediate result. When the FPU performs any operation, the calculation is carried out using extended-precision inputs, and the intermediate result is calculated produce infinite precision. After ...
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Rounding the Result The FPU supports the four rounding modes specified by the IEEE 754 standard. These modes are round to nearest (RN), round toward zero (RZ), round toward plus infinity (RP), and round toward minus infinity (RM). The ...
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Instruction Set Summary RN GUARD AND LSB = 1, ROUND AND STICKY = 0 OR GUARD = 1 ROUND OR STICKY = 1 ADD 1 TO LSB SHIFT MANTISSA RIGHT 1 BIT, ADD 1 TO EXPONENT Figure 3-2. Rounding Algorithm ...
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The following tie-case example shows how the 67-bit mantissa allows the FPU to meet the error bound of the IEEE specification: Result Intermediate Rounded-to-Nearest The LSB of the rounded result does not increment ...
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Instruction Set Summary 3.6.1 Underflow, Round, Overflow During the calculation of an arithmetic result, the FPU arithmetic logic unit (ALU) has more precision and range than the 80-bit extended precision format. However, the final result of these operations is an ...
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Data Type + Normalized or Denormalized – Normalized or Denormalized + 0 – Infinity – Infinity + NAN – NAN The inclusion of the NAN data type in the IEEE floating-point number system requires each conditional test to ...
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Instruction Set Summary When using the IEEE nonaware tests, the user receives a BSUN exception whenever a branch is attempted and the NAN condition code bit is set, unless the branch is an FBEQ or an FBNE. If the BSUN ...
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Table 3-23. Floating-Point Conditional Tests Mnemonic Definition EQ Equal NE Not Equal GT Greater Than NGT Not Greater Than GE Greater Than or Equal NGE Not Greater Than or Equal LT Less Than NLT Not Less Than LE Less Than ...
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Instruction Set Summary 3.7 INSTRUCTION DESCRIPTIONS Section and 7 contain detailed information about each instruction in the M68000 family instruction set. Each section arranges the instruction in alphabetical order by instruction mnemonic and includes descriptions of the ...
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INSTRUCTION NAME APPLICABLE PROCESSORS OPERATION DESCRIPTION INSTRUCTION'S ASSEMBLER SYNTAX SIZE ATRIBUTE TEXT DESCRIPTION OF INSTRUCTION OPERATION APPLICABLE RESULT OF FLOATING-POINT OPERATION EFFECTS ON INTEGER CONDITION CODES OR FLOATING-POINT STATUS REGISTER INSTRUCTION FORMAT DEFINITIONS AND ALLOWED VALUES FOR THE INSTRUCTION FORMAT ...
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SECTION 4 INTEGER INSTRUCTIONS This section contains detailed information about the integer instructions for the M68000 family. A detailed discussion of each instruction description is arranged in alphabetical order by instruction mnemonic. Each instruction description identifies the differences among the ...
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Integer Instructions ABCD Operation: Source10 + Destination10 + X Assembler ABCD Dy,Dx Syntax: ABCD – (Ay), – (Ax) Attributes: Size = (Byte) Description: Adds the source operand to the destination operand along with the extend bit, and stores the result ...
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ABCD Instruction Format REGISTER Rx Instruction Fields: Register Rx field—Specifies the destination register specifies a data register specifies an address register for the ...
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Integer Instructions ADD Operation: Source + Destination Assembler ADD < ea > ,Dn Syntax: ADD Dn, < ea > Attributes: Size = (Byte, Word, Long) Description: Adds the source operand to the destination operand using binary addition and stores the ...
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ADD Instruction Fields: Register field—Specifies any of the eight data registers. Opmode field Byte Word Long 000 001 100 101 Effective Address field—Determines addressing mode the location specified is a source operand, all addressing modes can be used ...
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Integer Instructions ADD b. If the location specified is a destination operand, only memory alterable addressing modes can be used as listed in the following tables: Addressing Mode Mode Dn An (An) (An) + – (An) (d ,An ...
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ADDA Operation: Source + Destination Assembler Syntax: ADDA < ea > Attributes: Size = (Word, Long) Description: Adds the source operand to the destination address register and stores the result in the address register. The size of the ...
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Integer Instructions ADDA Effective Address field—Specifies the source operand. All addressing modes can be used as listed in the following tables: Addressing Mode Mode Dn An (An) (An) + – (An) (d ,An ,An,Xn) 8 MC68020, MC68030, and ...
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ADDI Operation: Immediate Data + Destination Assembler Syntax: ADDI # < data > , < ea > Attributes: Size = (Byte, Word, Long) Description: Adds the immediate data to the destination operand and stores the result in the destination location. ...
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Integer Instructions ADDI Instruction Fields: Size field—Specifies the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed ...
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ADDQ Operation: Immediate Data + Destination Assembler Syntax: ADDQ # < data > , < ea > Attributes: Size = (Byte, Word, Long) Description: Adds an immediate value of one to eight to the operand at the destination location. The ...
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Integer Instructions ADDQ Instruction Fields: Data field—Three bits of immediate data representing eight values (0 – 7), with the immediate value zero representing a value of eight. Size field—Specifies the size of the operation. 00— Byte operation 01— Word operation ...
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ADDX Operation: Source + Destination + X Assembler ADDX Dy,Dx Syntax: ADDX – (Ay), – (Ax) Attributes: Size = (Byte, Word, Long) Description: Adds the source operand and the extend bit to the destination operand and stores the result in ...
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Integer Instructions ADDX Instruction Format REGISTER Rx Instruction Fields: Register Rx field—Specifies the destination register specifies a data register specifies an address register ...
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AND Operation: Source L Destination Assembler AND < ea > ,Dn Syntax: AND Dn, < ea > Attributes: Size = (Byte, Word, Long) Description: Performs an AND operation of the source operand with the destination operand and stores the result ...
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Integer Instructions AND Effective Address field—Determines addressing mode the location specified is a source operand, only data addressing modes can be used as listed in the following tables: Addressing Mode Mode Dn An (An) (An) + – (An) ...
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AND b. If the location specified is a destination operand, only memory alterable address- ing modes can be used as listed in the following tables: Addressing Mode Mode Dn An (An) (An) + – (An) (d ,An ,An,Xn) ...
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Integer Instructions ANDI Operation: Immediate Data Assembler Syntax: ANDI # < data > , < ea > Attributes: Size = (Byte, Word, Long) Description: Performs an AND operation of the immediate data with the destination operand and stores the result ...
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ANDI Instruction Fields: Size field—Specifies the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the ...
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Integer Instructions ANDI to CCR Operation: Source Assembler Syntax: ANDI # < data > ,CCR Attributes: Size = (Byte) Description: Performs an AND operation of the immediate operand with the condition codes and stores the result in the low-order byte ...
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ASL, ASR Operation: Destination Shifted By Count Assembler ASd Dx,Dy Syntax: ASd # < data > ,Dy ASd < ea > where d is direction Attributes: Size = (Byte, Word, Long) Description: Arithmetically shifts the bits of ...
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Integer Instructions ASL, ASR For ASR, the operand is shifted right; the number of positions shifted is the shift count. Bits shifted out of the low-order bit go to both the carry and the extend bits; the sign bit (MSB) ...
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ASL, ASR dr field—Specifies the direction of the shift. 0 — Shift right 1 — Shift left Size field—Specifies the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation i/r field If i/r ...
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Integer Instructions ASL, ASR Effective Address field—Specifies the operand to be shifted. Only memory alterable addressing modes can be used as listed in the following tables: Addressing Mode Mode Dn An (An) (An) + – (An) (d ,An ...
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Bcc Operation: If Condition True Then Assembler Syntax: Bcc < label > Attributes: Size = (Byte, Word, Long*) *(MC68020, MC68030, and MC68040 only) Description: If the specified condition is true, program execution continues at location (PC) + ...
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Integer Instructions Bcc Instruction Format 16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00 32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF Instruction Fields: Condition field—The binary code for one of the conditions listed ...
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BCHG Operation: TEST ( < number > of Destination) TEST ( < number > of Destination) Assembler BCHG Dn, < ea > Syntax: BCHG # < data > , < ea > Attributes: Size = (Byte, Long) Description: Tests a ...
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Integer Instructions BCHG Instruction Format: BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER REGISTER Instruction Fields: Register field—Specifies the data register that contains the bit number. Effective Address field—Specifies the destination location. ...
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BCHG Instruction Format: BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA Instruction Fields: Effective Address field—Specifies the destination location. Only data alterable addressing modes can be ...
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Integer Instructions BCLR Operation: TEST ( < bit number > of Destination) tination Assembler BCLR Dn, < ea > Syntax: BCLR # < data > , < ea > Attributes: Size = (Byte, Long) Description: Tests a bit in the ...
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BCLR Instruction Format: BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER REGISTER Instruction Fields: Register field—Specifies the data register that contains the bit number. Effective Address field—Specifies the destination location. Only data ...
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Integer Instructions BCLR Instruction Format: BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA Instruction Fields: Effective Address field—Specifies the destination location. Only data alterable addressing modes ...
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BFCHG Operation: TEST ( < bit field > of Destination) Assembler Syntax: BFCHG < ea > {offset:width} Attributes: Unsized Description: Sets the condition codes according to the value in a bit field at the specified effective address, then complements the ...
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Integer Instructions BFCHG Instruction Fields: Effective Address field—Specifies the base location for the bit field. Only data register direct or control alterable addressing modes can be used as listed in the following table: Addressing Mode Mode Dn An (An) (An) ...
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BFCLR Operation: 0 < bit field > of Destination Assembler Syntax: BFCLR < ea > {offset:width} Attributes: Unsized Description: Sets condition codes according to the value in a bit field at the specified effective address and clears the field. The ...
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Integer Instructions BFCLR Instruction Fields: Effective Address field—Specifies the base location for the bit field. Only data register direct or control alterable addressing modes can be used as listed in the following table: Addressing Mode Mode Dn An (An) (An) ...
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BFEXTS Operation: < bit field > of Source Assembler Syntax: BFEXTS < ea > {offset:width},Dn Attributes: Unsized Description: Extracts a bit field from the specified effective address location, sign extends to 32 bits, and loads the result into the destination ...
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Integer Instructions BFEXTS Instruction Fields: Effective Address field—Specifies the base location for the bit field. Only data register direct or control addressing modes can be used as listed in the following table: Addressing Mode Mode Dn An (An) (An) + ...
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BFEXTS Width field—Specifies the field width, depending on Dw the width field is an immediate operand; operand values in the range of 1 – 31 specify a field width of 1 – 31, and a value ...
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Integer Instructions BFEXTU Operation: < bit offset > of Source Assembler Syntax: BFEXTU < ea > {offset:width},Dn Attributes: Unsized Description: Extracts a bit field from the specified effective address location, zero extends to 32 bits, and loads the results into ...
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BFEXTU Instruction Fields: Effective Address field—Specifies the base location for the bit field. Only data register direct or control addressing modes can be used as listed in the following table: Addressing Mode Mode Dn An (An) (An) + – (An) ...
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Integer Instructions BFEXTU Width field—Specifies the field width, depending on Dw the width field is an immediate operand; operand values in the range of 1 – 31 specify a field width of 1 – 31, and ...
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BFFFO Operation: < bit offset > of Source Bit Scan Assembler Syntax: BFFFO < ea > {offset:width},Dn Attributes: Unsized Description: Searches the source operand for the most significant bit that is set to a value of one. The bit offset ...
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Integer Instructions BFFFO Instruction Fields: Effective Address field—Specifies the base location for the bit field. Only data register direct or control addressing modes can be used as listed in the following table: Addressing Mode Mode Dn An (An) (An) + ...
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BFFFO Width field—Specifies the field width, depending on Dw the width field is an immediate operand; operand values in the range of 1 – 31 specify a field width of 1 – 31, and a value ...
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Integer Instructions BFINS Operation: Dn < bit field > of Destination Assembler Syntax: BFINS Dn, < ea > {offset:width} Attributes: Unsized Description: Inserts a bit field taken from the low-order bits of the specified data register into a bit field ...
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BFINS Instruction Fields: Effective Address field—Specifies the base location for the bit field. Only data register direct or control alterable addressing modes can be used as listed in the following table: Addressing Mode Mode Dn An (An) (An) + – ...
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Integer Instructions BFINS Width field—Specifies the field width, depending on Dw the width field is an immediate operand; operand values in the range of 1 – 31 specify a field width of 1 – 31, and ...
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BFSET Operation: 1 < bit field > of Destination Assembler Syntax: BFSET < ea > {offset:width} Attributes: Unsized Description: Sets the condition codes according to the value in a bit field at the specified effective address, then sets each bit ...
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Integer Instructions BFSET Instruction Fields: Effective Address field—Specifies the base location for the bit field. Only data register direct or control alterable addressing modes can be used as listed in the following table: Addressing Mode Mode Dn An (An) (An) ...
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BFTST Operation: < bit field > of Destination Assembler Syntax: BFTST < ea > {offset:width} Attributes: Unsized Description: Sets the condition codes according to the value in a bit field at the specified effective address location. The field offset and ...
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Integer Instructions BFTST Instruction Fields: Effective Address field—Specifies the base location for the bit field. Only data register direct or control addressing modes can be used as listed in the following table: Addressing Mode Mode Dn An (An) (An) + ...
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BKPT (MC68EC000, MC68010, MC68020, MC68030, MC68040, CPU32) Operation: Run Breakpoint Acknowledge Cycle; TRAP As Illegal Instruction Assembler Syntax: BKPT # < data > Attributes: Unsized Description: For the MC68010, a breakpoint acknowledge bus cycle is run with function codes driven ...
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Integer Instructions BKPT (MC68EC000, MC68010, MC68020, Condition Codes: Not affected. Instruction Format Instruction Field: Vector field—Contains the immediate data, a value in the range of 0 – 7. This is ...
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BRA Operation Assembler Syntax: BRA < label > Attributes: Size = (Byte, Word, Long*) *(MC68020, MC68030, MC68040 only) Description: Program execution continues at location (PC) + displacement. The program counter contains the address of the instruction ...
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Integer Instructions BSET Operation: TEST ( < bit number > of Destination) tination Assembler BSET Dn, < ea > Syntax: BSET # < data > , < ea > Attributes: Size = (Byte, Long) Description: Tests a bit in the ...
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BSET Instruction Format: BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER REGISTER Instruction Fields: Register field—Specifies the data register that contains the bit number. Effective Address field—Specifies the destination location. Only data ...
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Integer Instructions BSET Instruction Format: BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA Instruction Fields: Effective Address field—Specifies the destination location. Only data alterable addressing modes ...
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BSR Operation: SP – 4 Assembler Syntax: BSR < label > Attributes: Size = (Byte, Word, Long*) *(MC68020, MC68030, MC68040 only) Description: Pushes the long-word address of the instruction immediately following the BSR instruction onto the system stack. The program ...
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Integer Instructions BSR Instruction Fields: 8-Bit Displacement field—Twos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed. 16-Bit Displacement field—Used for a larger displacement when the 8-bit displacement is equal to ...
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BTST Operation: TEST ( < bit number > of Destination) Assembler BTST Dn, < ea > Syntax: BTST # < data > , < ea > Attributes: Size = (Byte, Long) Description: Tests a bit in the destination operand and ...
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Integer Instructions BTST Instruction Format: BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER REGISTER Instruction Fields: Register field—Specifies the data register that contains the bit number. Effective Address field—Specifies the destination location. ...
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BTST Instruction Format: BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA Instruction Fields: Effective Address field—Specifies the destination location. Only data addressing modes can be used ...
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Integer Instructions CALLM Operation: Save Current Module State on Stack; Load New Module State from Destination Assembler Syntax: CALLM # < data > , < ea > Attributes: Unsized Description: The effective address of the instruction is the location of ...
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CALLM Instruction Fields: Effective Address field—Specifies the address of the module descriptor. Only control addressing modes can be used as listed in the following table: Addressing Mode Mode Dn An (An) (An) + – (An) (d ,An ,An,Xn) ...
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Integer Instructions CAS CAS2 Compare and Swap with Operand Operation: CAS Destination – Compare Operand If Z, Update Operand Else Destination CAS2 Destination 1 – Compare Destination 2 – Compare Update 1 Else Destination ...
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CAS CAS2 Compare and Swap with Operand Instruction Format Instruction Fields: Size field—Specifies the size of the operation. 01 — Byte operation 10 — Word ...
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Integer Instructions CAS CAS2 Compare and Swap with Operand Instruction Format D/A1 Rn1 0 D/A2 Rn2 0 Instruction Fields: Size field—Specifies the size of the operation. 10 — Word operation ...
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CHK Check Register Against Bounds Operation < > Source Then TRAP Assembler Syntax: CHK < ea > ,Dn Attributes: Size = (Word, Long*) *(MC68020, MC68030, MC68040 only) Description: Compares the value in the data register ...
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Integer Instructions CHK Check Register Against Bounds Instruction Fields: Register field—Specifies the data register that contains the value to be checked. Size field—Specifies the size of the operation. 11— Word operation 10— Long operation Effective Address field—Specifies the upper bound ...
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CHK2 Check Register Against Bounds (MC68020, MC68030, MC68040, CPU32) Operation < > UB Then TRAP Assembler Syntax: CHK2 < ea > ,Rn Attributes: Size = (Byte, Word, Long) Description: Compares the value ...
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Integer Instructions CHK2 Check Register Against Bounds (MC68020, MC68030, MC68040, CPU32) Instruction Format D/A REGISTER 1 Instruction Fields: Size field—Specifies the size of the operation. 00 — Byte operation 01 ...
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CLR Operation: 0 Destination Assembler Syntax: CLR < ea > Attributes: Size = (Byte, Word, Long) Description: Clears the destination operand to zero. The size of the operation may be specified as byte, word, or long. Condition Codes ...
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Integer Instructions CLR Instruction Fields: Size field—Specifies the size of the operation. 00— Byte operation 01— Word operation 10— Long operation Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following ...
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CMP Operation: Destination – Source Assembler Syntax: CMP < ea > Attributes: Size = (Byte, Word, Long) Description: Subtracts the source operand from the destination data register and sets the condition codes according to the result; the data ...
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Integer Instructions CMP Effective Address field—Specifies the source operand. All addressing modes can be used as listed in the following tables: Addressing Mode Mode Dn An* (An) (An) + – (An) (d ,An ,An,Xn) 8 MC68020, MC68030, and ...
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CMPA Operation: Destination – Source Assembler Syntax: CMPA < ea > Attributes: Size = (Word, Long) Description: Subtracts the source operand from the destination address register and sets the condition codes according to the result; the address register ...
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Integer Instructions CMPA Instruction Fields: Register field—Specifies the destination address register. Opmode field—Specifies the size of the operation. 011— Word operation; the source operand is sign-extended to a long operand, and the operation is performed on the address register using ...
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CMPI Operation: Destination – Immediate Data Assembler Syntax: CMPI # < data > , < ea > Attributes: Size = (Byte, Word, Long) Description: Subtracts the immediate data from the destination operand and sets the condition codes according to the ...
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Integer Instructions CMPI Instruction Fields: Size field—Specifies the size of the operation. 00 — Byte operation 01 — Word operation 10 — Long operation Effective Address field—Specifies the destination operand. Only data addressing modes can be used as listed in ...
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CMPM Operation: Destination – Source Assembler Syntax: CMPM (Ay) + ,(Ax) + Attributes: Size = (Byte, Word, Long) Description: Subtracts the source operand from the destination operand and sets the condition codes according to the results; the destination location is ...
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Integer Instructions CMP2 Compare Register Against Bounds (MC68020, MC68030, MC68040, CPU32) Operation: Compare Rn < > UB and Set Condition Codes Assembler Syntax: CMP2 < ea > ,Rn Attributes: Size = (Byte, Word, Long) Description: Compares the ...
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CMP2 Compare Register Against Bounds (MC68020, MC68030, MC68040, CPU32) Instruction Format D/A REGISTER 0 Instruction Fields: Size field—Specifies the size of the operation. 00 — Byte operation 01 — Word ...
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Integer Instructions cpBcc Branch on Coprocessor Condition Operation: If cpcc True Then Scan Assembler Syntax: cpBcc < label > Attributes: Size = (Word, Long) Description: If the specified coprocessor condition is true, program execution continues at location ...
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Test Coprocessor Condition Operation: If cpcc False Then (Dn – 1 Assembler Syntax: cpDBcc Dn, < label > Attributes: Size = (Word) Description: If the specified coprocessor condition is true, execution continues with the next instruction. Otherwise, the low-order ...
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Integer Instructions cpGEN Coprocessor General Function Operation: Pass Command Word to Coprocessor Assembler Syntax: cpGEN < parameters as defined by coprocessor > Attributes: Unsized Description: Transfers the command word that follows the operation word to the specified coprocessor. The coprocessor ...
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Set on Coprocessor Condition Operation: If cpcc True Then 1s Else 0s Assembler Syntax: cpScc < ea > Attributes: Size = (Byte) Description: Tests the specified coprocessor condition code. If the condition is true, the byte specified by the ...
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Integer Instructions cpScc Set on Coprocessor Condition Instruction Fields: Coprocessor ID field—Identifies the coprocessor for this operation. Coprocessor ID of 000 results in an F-line exception for the MC68030. Effective Address field—Specifies the destination location. Only data alterable addressing modes ...
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Trap on Coprocessor Condition Operation: If cpcc True Then TRAP Assembler cpTRAPcc Syntax: cpTRAPcc # < data > Attributes: Unsized or Size = (Word, Long) Description: Tests the specified coprocessor condition code; if the selected coprocessor condition is true, ...
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Integer Instructions DBcc Test Condition, Decrement, and Branch Operation: If Condition False Then (Dn – 1 Assembler Syntax: DBcc Dn, < label > Attributes: Size = (Word) Description: Controls a loop of instructions. The parameters are a condition code, a ...
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DBcc Test Condition, Decrement, and Branch Instruction Format Instruction Fields: Condition field—The binary code for one of the conditions listed in the table. Register field—Specifies the data register used as the ...
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Integer Instructions DIVS, DIVSL Operation: Destination Assembler DIVS.W < ea > ,Dn32/16 Syntax: *DIVS.L < ea > ,Dq *DIVS.L < ea > ,Dr:Dq *DIVSL.L < ea > ,Dr:Dq *Applies to MC68020, MC68030, MC68040, CPU32 only Attributes: Size = (Word, Long) ...
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DIVS, DIVSL Instruction Format REGISTER Instruction Fields: Register field—Specifies any of the eight data registers. This field always specifies the destination operand. Effective Address field—Specifies the source operand. Only data alterable ...
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Integer Instructions DIVS, DIVSL Instruction Format REGISTER Dq 1 Instruction Fields: Effective Address field—Specifies the source operand. Only data alterable addressing modes can be used as listed in the ...
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DIVS, DIVSL Register Dr field—After the division, this register contains the 32-bit remainder and Dq are the same register, only the quotient is returned. If the size field is 1, this field also specifies the data register that ...
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Integer Instructions DIVU, DIVUL Operation: Destination Assembler DIVU.W < ea > ,Dn32/16 Syntax: *DIVU.L < ea > ,Dq *DIVU.L < ea > ,Dr:Dq *DIVUL.L < ea > ,Dr:Dq *Applies to MC68020, MC68030, MC68040, CPU32 only. Attributes: Size = (Word, Long) ...