MC68EC000EI16 Freescale Semiconductor, MC68EC000EI16 Datasheet - Page 25

no-image

MC68EC000EI16

Manufacturer Part Number
MC68EC000EI16
Description
IC MPU 32BIT 16MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68EC000EI16

Processor Type
M680x0 32-Bit
Speed
16MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68EC000EI16
Manufacturer:
FREESCALE
Quantity:
450
Part Number:
MC68EC000EI16
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MC68EC000EI16
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68EC000EI16R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Introduction
1.4 INTEGER DATA FORMATS
The operand data formats supported by the integer unit, as listed in Table 1-3, include those
supported by the MC68030 plus a new data format (16-byte block) for the MOVE16
instruction. Integer unit operands can reside in registers, memory, or instructions
themselves. The operand size for each instruction is either explicitly encoded in the
instruction or implicitly defined by the instruction operation.
1-14
Address Mask
E—Enable
S—Supervisor/User Mode
U1, U2—User Page Attributes
CM—Cache Mode
W—Write Protect
This 8-bit field contains a mask for the address base field. Setting a bit in this field causes
This bit enables and disables transparent translation/access control of the block defined
This field specifies the use of the FC2 in matching an address.
The MC68040, MC68E040, MC68LC040 do not interpret these user-defined bits. If an
This field selects the cache mode and access serialization for a page as follows:
This bit indicates if the block is write protected. If set, write and read-modify-write
the corresponding bit in the address base field to be ignored. Blocks of memory larger
than 16 Mbytes can be transparently translated/access controlled by setting some logical
address mask bits to ones. The low-order bits of this field normally are set to define con-
tiguous blocks larger than 16 Mbytes, although this not required.
by this register.
external bus transfer results from the access, U0 and U1 are echoed to the UPA0 and
UPA1 signals, respectively.
accesses are aborted as if the resident bit in a table descriptor were clear.
00 = Match only if FC2 is 0 (user mode access)
01 = Match only if FC2 is 1 (supervisor mode access)
1X = Ignore FC2 when matching
00 = Cachable, Writethrough
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
0 = Transparent translation/access control disabled
1 = Transparent translation/access control enabled
0 = Read and write accesses permitted
1 = Write accesses not permitted
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA

Related parts for MC68EC000EI16