MC68EC000EI16 Freescale Semiconductor, MC68EC000EI16 Datasheet - Page 77

• Manufacturer Part Number: MC68EC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Instruction Set Summary
3.1.2 Integer Arithmetic Instructions
The integer arithmetic operations include four basic operations: ADD, SUB, MUL, and DIV.
They also include CMP, CMPM, CMP2, CLR, and NEG. The instruction set includes ADD,
CMP, and SUB instructions for both address and data operations with all operand sizes valid
for data operations. Address operands consist of 16 or 32 bits. The CLR and NEG
instructions apply to all sizes of data operands. Signed and unsigned MUL and DIV
instructions include:
3-6
NOTE: A register list includes any combination of the eight floating-point data registers or any combination of
Instruction
• Word multiply to produce a long-word product.
• Long-word multiply to produce a long-word or quad-word product.
• Long word divided by a word divisor (word quotient and word remainder).
• Long word or quad word divided by a long-word divisor (long-word quotient and long-
FSMOVE,
FDMOVE
FMOVEM
MOVE16
MOVEM
MOVEA
MOVEQ
FMOVE
MOVEP
word remainder).
MOVE
UNLK
LINK
EXG
PEA
LEA
three control registers (FPCR, FPSR, and FPIAR). If a register list mask resides in a data register, only
floating-point data registers may be specified.
Operand Syntax
<ea>,<list>
<list>
Dn, (d
(d
#<data>,Dn
<ea>,<ea>
<ea>,<ea>
FPm,<ea>
<ea>,FPcr
FPcr,<ea>
<ea>,FPn
<ea>,FPn
FPm,FPn
FPm,FPn
<ea>,Dn
Dn,<ea>
<ea>,An
An,#<d>
<ea>,An
list,<ea>
<ea>,list
16
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Rn, Rn
<ea>
,An),Dn
An
Table 3-2. Data Movement Operation Format
1
16
,<ea>
,An)
1
B, W, L, S, D, X, P
B, W, L, S, D, X, P
Operand Size
B, W, L, S, D, X
16, 32
16, 32
8, 16, 32
16 bytes
8
16, 32
16, 32
16, 32
32, X
32, X
32
32
32
32
32
32
X
X
X
X
32
32
32
Rn
Source
Source
double precision.
Listed Registers
Source
<ea>
SP – 4
Source
Aligned 16-Byte Block
Listed Registers
Source
Dn 31–24
(An + d
Immediate Data
SP – 4
An
Dn 15–8
(An + d
SP; (SP)
n
n
)
An
Rn
+ 4)
SP; An
SP; <ea>
Destination
Destination; round destination to single or
Listed Registers
Destination
Listed Registers
(An + d
Dn 31–24; (An + d
(An + d
Dn 15–8; (An + d
An; SP + 4
Destination
Destination
Destination
n
n
(SP); SP
); Dn 23–16
+ 4); Dn 7–0
Operation
(SP)
Destination
n
+ 2)
SP
An, SP + D
n
+ 6)
(An + d
(An + d
Dn 23–16;
Dn 7–0
MOTOROLA
n
n
+ 2);
+ 6)
SP