MC68EC000EI16 Freescale Semiconductor, MC68EC000EI16 Datasheet - Page 489

• Manufacturer Part Number: MC68EC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PFLUSH
Operation:
Assembler
Syntax:
Syntax:
Syntax:
Attributes:
Description: Invalidates address translation cache entries in both the instruction and data
Condition Codes:
MOTOROLA
Not affected.
address translation caches. The instruction has two forms. The PFLUSHA instruction
invalidates all entries. The PFLUSH (An) instruction invalidates the entry in each
address translation cache which matches the logical address in An and the specified
function code.
The function code for PFLUSH is specified in the destination function code register.
Destination function code values of 1 or 2 will result in flushing of user address trans-
lation cache entries in both address translation caches; whereas, values of 5 or 6 will
result in flushing of supervisor address translation cache entries. PFLUSH is undefined
for destination function code values of 0, 3, 4, and 7 and may cause flushing of an
unexpected entry.
The PFLUSHN and PFLUSHAN instructions have a global option specified and invali-
date only nonglobal entries. For example, if only page descriptors for operating system
code have the global bit set, these two PFLUSH variants can be used to flush only user
address translation cache entries during task swaps.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Supervisor State
Else TRAP
PFLUSH (An)
PFLUSHN (An)
PFLUSHA
PFLUSHAN
Unsized
Then Invalidate Instruction and Data ATC Entries for Destination
Address
(MC68040, MC68LC040)
Flush ATC Entries
Supervisor (Privileged) Instructions
PFLUSH
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