MC68EC000EI16 Freescale Semiconductor, MC68EC000EI16 Datasheet - Page 546

• Manufacturer Part Number: MC68EC000EI16
• Description: IC MPU 32BIT 16MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

CPU32 Instructions
TBLS
TBLSN
Operation:
Assembler
Syntax:
Attributes:
Description: The TBLS and TBLSN instructions allow the efficient use of piecewise linear
7-6
compressed data tables to model complex functions. The TBLS instruction has two
modes of operation: table lookup and interpolate mode and data register interpolate
mode.
For table lookup and interpolate mode, data register Dx 15 – 0 contains the
independent variable X. The effective address points to the start of a signed byte, word,
or long-word table containing a linearized representation of the dependent variable, Y,
as a function of X. In general, the independent variable, located in the low-order word
of Dx, consists of an 8-bit integer part and an 8-bit fractional part. An assumed radix
point is located between bits 7 and 8. The integer part, Dx 15 – 8, is scaled by the
operand size and is used as an offset into the table. The selected entry in the table is
subtracted from the next consecutive entry. A fractional portion of this difference is
taken by multiplying by the interpolation fraction, Dx 7 – 0 .The adjusted difference is
then added to the selected table entry. The result is returned in the destination data
register, Dx.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Rounded:
Unrounded:
Where ENTRY(n) and ENTRY(n + 1) are either:
TBLS. < size > < ea > ,Dx
TBLSN. < size > < ea > ,Dx
TBLS. < size > Dym:Dyn, Dx
TBLSN. < size > Dym:Dyn, Dx
Size = (Byte, Word, Long)
Table Lookup and Interpolate (Signed)
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0} 256
ENTRY(n) x 256 + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0}
1. Consecutive entries in the table pointed to by the < ea > and
2. The registers Dym, Dyn respectively.
indexed by Dx 15 – 8
(CPU32)
SIZE or;
Result not rounded
Result rounded
Result not rounded
Result rounded
TBLSN
TBLS
MOTOROLA
Dx
Dx